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Performance analysis and design of a logic simulation machine
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Source International Symposium on Computer Architecture archive
Proceedings of the 14th annual international symposium on Computer architecture table of contents
Pittsburgh, Pennsylvania, United States
Pages: 46 - 55  
Year of Publication: 1987
ISBN:0-8186-0776-9
Authors
K. Wong  Computer and Communications Research Center, Washington University, St. Louis, MO
M. A. Franklin  Computer and Communications Research Center, Washington University, St. Louis, MO
Sponsor
SIGARCH: ACM Special Interest Group on Computer Architecture
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 9,   Downloads (12 Months): 17,   Citation Count: 4
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ABSTRACT

The high costs associated with logic simulation of large VLSI circuits has led to the need for new computer architectures tailored to the simulation task. Such architectures have the potential for significant speed-ups over software-based logic simulators executing on standard sequential computers. This paper presents a model of one class of multiprocessor simulation architectures and compares the performance of some of these machines using data obtained from simulations of VLSI circuits. In addition, we discuss the implications of our results on machine design and examine the sensitivity of the model to variations in circuit characteristics.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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M. A. Franklin, D. F. Warm, and K. F. Wont, "Parallel Machines and Algorithms for Discrete- Event Simulation," Proc. 1984 Int. Conf. on Parallel Processing, Aug. 1984, pp. 449-458.
 
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M. Abramovici, Y. H. Levendel, and P. R. Menon, "A Logic Simulation Machine," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems CAD-2:2 (Apr. 1983), pp. 82-94.
 
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R. D. Chamberlain, "Lsim: A Gate-Switch Level Logic Simulator," M.S. Thesis, Dept. of Computer Science, Washington University, St. Louis, MO., May 1985.
 
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R. D. Chamberlain and M. A. Franklin, "Collecting Data About Logic Simulation," IEEE Trans. on Computer-Aided Design CAD-5:3 (July 1986), pp. 405-412.
 
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