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ABSTRACT
The high costs associated with logic simulation of large VLSI circuits has led to the need for new computer architectures tailored to the simulation task. Such architectures have the potential for significant speed-ups over software-based logic simulators executing on standard sequential computers. This paper presents a model of one class of multiprocessor simulation architectures and compares the performance of some of these machines using data obtained from simulations of VLSI circuits. In addition, we discuss the implications of our results on machine design and examine the sensitivity of the model to variations in circuit characteristics.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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[doi> 10.1145/317825.317912]
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CITED BY 4
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S. Patil , P. Banerjee , C. Polychronopoulos, Efficient circuit partitioning algorithms for parallel logic simulation, Proceedings of the 1989 ACM/IEEE conference on Supercomputing, p.361-370, November 12-17, 1989, Reno, Nevada, United States
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