Power estimation for architectural exploration of HW/SW communication on system-level buses

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Power estimation for architectural exploration of HW/SW communication on system-level buses

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International Conference on Hardware Software Codesign archive
Proceedings of the seventh international workshop on Hardware/software codesign table of contents

Rome, Italy

Pages: 152 - 156

Year of Publication: 1999

ISBN:1-58113-132-1

Authors

William Fornaciari	Politecnico di Milano, Milan, Italy
Donatella Sciuto	Politecnico di Milano, Milan, Italy
Christina Silvano	CEFRIEL, Milan, Italy

Sponsors

IEEE-CS : Computer Society
IFIP : International Federation for Information Processing
SIGSOFT: ACM Special Interest Group on Software Engineering
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 11, Citation Count: 19

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	2	S. Ramprasad, N.R. Shanbhag, I.N. Hajj, "Signal Coding for Low Power. Fundamental limits and Practical Realizations," ISCAS98:1998 Int. Syrup. on Circuits and Systema, Monterey, CA 1998.
	3	Preeti R. Panda , Nikil D. Dutt, Reducing Address Bus Transitions for Low Power Memory Mapping, Proceedings of the 1996 European conference on Design and Test, p.63, March 11-14, 1996
	4	Mircea R. Stan , Wayne P. Burleson, Bus-invert coding for low-power I/O, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.3 n.1, p.49-58, March 1995 [doi>10.1109/92.365453]
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	7	L. Benini , G. De Micheli , E. Macii , D. Sciuto , C. Silvano, Address bus encoding techniques for system-level power optimization, Proceedings of the conference on Design, automation and test in Europe, p.861-867, February 23-26, 1998, Le Palais des Congrés de Paris, France
	8	Luca Benini , Giovanni De Mecheli , Enrico Macii , Massimo Poncino , Stefano Quer, Power optimization of core-based systems by address bus encoding, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.6 n.4, p.554-562, Dec. 1998 [doi>10.1109/92.736127]
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	11	Yanbing Li , Jörg Henkel, A framework for estimation and minimizing energy dissipation of embedded HW/SW systems, Proceedings of the 35th annual conference on Design automation, p.188-193, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277097]
	12	John L. Hennessy , David A. Patterson, Computer architecture (2nd ed.): a quantitative approach, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1996
	13	C.Silvano, "Power Estimation and Optimization Methdologies for Digital Circuits And Systems", Ph.D. Thesis, University of Brescia, Italy, Dec. 1998.
	14	Patrick Hicks , Matthew Walnock , Robert Michael Owens, Analysis of power consumption in memory hierarchies, Proceedings of the 1997 international symposium on Low power electronics and design, p.239-242, August 18-20, 1997, Monterey, California, United States [doi>10.1145/263272.263342]

CITED BY 19

	Tony Givargis , Frank Vahid , Jörg Henkel, A hybrid approach for core-based system-level power modeling, Proceedings of the 2000 conference on Asia South Pacific design automation, p.141-146, January 2000, Yokohama, Japan
	Haris Lekatsas , Jörg Henkel , Wayne Wolf, Code compression for low power embedded system design, Proceedings of the 37th conference on Design automation, p.294-299, June 05-09, 2000, Los Angeles, California, United States
	Tony D. Givargis , Jörg Henkel , Frank Vahid, Interface and cache power exploration for core-based embedded system design, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.270-273, November 07-11, 1999, San Jose, California, United States
	Kanishka Lahiri , Anand Raghunathan , Sujit Dey, Fast system-level power profiling for battery-efficient system design, Proceedings of the tenth international symposium on Hardware/software codesign, May 06-08, 2002, Estes Park, Colorado
	Ki Wook Kim , Kwang Hyun Baek , Naresh Shanbhag , C. L. Liu , Sung Mo Kang, Coupling-driven signal encoding scheme for low-power interface design, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	K. Basu , A. Choudhary , J. Pisharath , M. Kandemir, Power protocol: reducing power dissipation on off-chip data buses, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
	Tony D. Givargis , Frank Vahid, Parameterized system design, Proceedings of the eighth international workshop on Hardware/software codesign, p.98-102, May 2000, San Diego, California, United States
	Marcus T. Schmitz , Bashir M. Al-Hashimi , Petru Eles, Iterative schedule optimization for voltage scalable distributed embedded systems, ACM Transactions on Embedded Computing Systems (TECS), v.3 n.1, p.182-217, February 2004
	Tony D. Givargis , Frank Vahid , Jörg Henkel, Fast cache and bus power estimation for parameterized system-on-a-chip design, Proceedings of the conference on Design, automation and test in Europe, p.333-339, March 27-30, 2000, Paris, France
	Rajeev Krishna , Scott Mahlke , Todd Austin, Memory system design space exploration for low-power, real-time speech recognition, Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 08-10, 2004, Stockholm, Sweden
	Claudio Talarico , Jerzy W. Rozenblit , Vinod Malhotra , Albert Stritter, A New Framework for Power Estimation of Embedded Systems, Computer, v.38 n.2, p.71-78, February 2005
	Kanishka Lahiri , Anand Raghunathan, Power analysis of system-level on-chip communication architectures, Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 08-10, 2004, Stockholm, Sweden
	Jörg Henkel , Yanbing Li, Avalanche: an environment for design space exploration and optimization of low-power embedded systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.4, p.454-468, August 2002
	Chun Liu , Anand Sivasubramaniam , Mahmut Kandemir, Optimizing bus energy consumption of on-chip multiprocessors using frequent values, Journal of Systems Architecture: the EUROMICRO Journal, v.52 n.2, p.129-142, February 2006
	Sujan Pandey , Manfred Glesner, Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Sujan Pandey , Manfred Glesner, Simultaneous on-chip bus synthesis and voltage scaling under random on-chip data traffic, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.10, p.1111-1124, October 2007
	Alexandru Andrei , Petru Eles , Zebo Peng , Marcus T. Schmitz , Bashir M. Al Hashimi, Energy optimization of multiprocessor systems on chip by voltage selection, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.3, p.262-275, March 2007
	A. Andrei , M. Schmitz , P. Eles , Z. Peng , B. M. Al Hashimi, Simultaneous communication and processor voltage scaling for dynamic and leakage energy reduction in time-constrained systems, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.362-369, November 07-11, 2004
	U. Neffe , K. Rothbart , Ch. Steger , R. Weiss , E. Rieger , A. Mühlberger, Energy Estimation Based on Hierarchical Bus Models for Power-Aware Smart Cards, Proceedings of the conference on Design, automation and test in Europe, p.30300, February 16-20, 2004