| The case for a configure-and-execute paradigm |
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International Conference on Hardware Software Codesign
archive
Proceedings of the seventh international workshop on Hardware/software codesign
table of contents
Rome, Italy
Pages: 59 - 63
Year of Publication: 1999
ISBN:1-58113-132-1
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Authors
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Frank Vahid
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Dept. of Computer Science and Eng., Univ. of California, Riverside, CA
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Tony Givargis
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Dept. of Computer Science and Eng., Univ. of California, Riverside, CA
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| Bibliometrics |
Downloads (6 Weeks): 5, Downloads (12 Months): 15, Citation Count: 12
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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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K. Baoy, DAC eview, EE Times, r, une 8, 1998, Issue 1011.
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Adrian Evans , Allan Silburt , Gary Vrckovnik , Thane Brown , Mario Dufresne , Geoffrey Hall , Tung Ho , Ying Liu, Functional verification of large ASICs, Proceedings of the 35th annual conference on Design automation, p.650-655, June 15-19, 1998, San Francisco, California, United States
[doi> 10.1145/277044.277210]
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A. de Geus. The IC Hits Midlifc Crisis - From Silicon to Systems, EE Times, Sep 30, 1998, Issue 1028.
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K. Kiefendorff. Transistor Budgets Go Ballistic. Microprocessor Report, Volume t2, Number 10, August 3, 1998, 14-181
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J. van Meerbergen, A. Timmer, J. Leijtan, F. Hatmsze, M. Strik. Experiences with Syslem Level Design for Consumer ICs, VLSI'98, pp 17-22.
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Midyear forecast - CEO Perspectives, EE Times, May 27, 1998, Issue 1009.
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B. Payne. Rapid Silicon Prototyping: Paradigm for Custom System-ona-Chip Design, httpJ/www.vlsi.com/velocity.
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J. Quigley. DAC Preview, EE Times, June 8, 1998, Issue 1011.
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J. Rabaey, A. Abnous, Y. lehikawa, IC Seno, M. Wan, Heterogeneous Reconfignrable Systems, IEI Workshop on Signal Processing Systems, 1997, pp 24-34.
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M. Satrafzadeh. Confab calls for flexible lab processes - layout gap could repeal Moore's law, EE Times, April 13, 1998, Issue 1002.
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Semiconductor Industry Association Roaflmap 1997, hrtp:ttnotea.sematech.org/ntrs/PublNTRg.nsf.
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Velocity product information, VI.,SI Technology Inc., http:/twww.vlsi.com/velocity.
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Virtual Socket Interface Association Architecture Document, http://www.vsi.org.
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Xilinx LogiCORE product information, Xilinx Corp., http:ttwww.xilinx.com.
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The UCR Dalton project: http:/twww.cs.ucr.edu/-dalton.
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CITED BY 12
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F. Vermeulen , F. Catthoor , D. Verkest , H. De Man, Extended design reuse trade-offs in hardware-software architecture mapping, Proceedings of the eighth international workshop on Hardware/software codesign, p.103-107, May 2000, San Diego, California, United States
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F. Vermeulen , L. Nachtergaele , F. Catthoor , D. Verkest , H. De Man, Flexible hardware acceleration for multimedia oriented microprocessors, Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture, p.171-177, December 2000, Monterey, California, United States
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Tony D. Givargis , Frank Vahid , Jörg Henkel, Fast cache and bus power estimation for parameterized system-on-a-chip design, Proceedings of the conference on Design, automation and test in Europe, p.333-339, March 27-30, 2000, Paris, France
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