A performance comparison of contemporary DRAM architectures

ABSTRACT

In response to the growing gap between memory access time and processor speed, DRAM manufacturers have created several new DRAM architectures. This paper presents a simulation-based performance study of a representative group, each evaluated in a small system organization. These small-system organizations correspond to workstation-class computers and use on the order of 10 DRAM chips. The study covers Fast Page Mode, Extended Data Out, Synchronous, Enhanced Synchronous, Synchronous Link, Rambus, and Direct Rambus designs. Our simulations reveal several things: (a) current advanced DRAM technologies are attacking the memory bandwidth problem but not the latency problem; (b) bus transmission speed will soon become a primary factor limiting memory-system performance; (c) the post-L2 address stream still contains significant locality, though it varies from application to application; and (d) as we move to wider buses, row access time becomes more prominent, making it important to investigate techniques to exploit the available locality to decrease access time.

REFERENCES

• 1: Luiz André Barroso , Kourosh Gharachorloo , Edouard Bugnion, Memory system characterization of commercial workloads, Proceedings of the 25th annual international symposium on Computer architecture, p.3-14, June 27-July 02, 1998, Barcelona, Spain
• 2: Dileep Bhandarkar , Jason Ding, Performance Characterization of the Pentium® Pro Processor, Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture, p.288, February 01-05, 1997
• 3: N. Bowman, et al. "Evaluation of existing architectures in IRAM systems." Work~shop on Mixing Logic and DRAM, June 1997.
• 4: D. Burger and T. M, Austin. "The SimpleScalar tool set, version 2.0." Tech. Rep. CS-1342, University of Wisconsin-Madison, June 1997.
• 5: Doug Burger , James R. Goodman , Alain Kägi, Memory bandwidth limitations of future microprocessors, Proceedings of the 23rd annual international symposium on Computer architecture, p.78-89, May 22-24, 1996, Philadelphia, Pennsylvania, United States
• 6: M. Charney, P. Coteus, P. Emma, J. Rivers, and J. Rogers. Private communication. 1999.
• 7: Richard Crisp, Direct Rambus Technology: The New Main Memory Standard, IEEE Micro, v.17 n.6, p.18-28, November 1997 [doi>10.1109/40.641593]
• 8: V. Cuppu and B. Jacob. "The performance of next-generation DRAM architectures." Tech. Rep. UMD-SCA-TR- 1999-1, University of Maryland Systems and Computer Architecture Group, March 1999.
• 9: Z. Cvetanovic , D. Bhandarkar, Characterization of alpha AXP performance using TP and SPEC workloads, Proceedings of the 21ST annual international symposium on Computer architecture, p.60-70, April 18-21, 1994, Chicago, Illinois, United States
• 10: ESDRAM. Enhanced SDRAM IM x 16. Enhanced Memory Systems, http :Hwww.edram. cona/products/datashects/16M e..sdmxn0298a, pd f, 1998.
• 11: Etch. Memory System Research at the University of Washington. The University of Washington, http'Jtetch.cs.washington.edu/, 1998.
• 12: L. Gwennap. "Alpha 21364 to ease memory bottleneck." MicroprocessorReport, vol. 12, no. 14, pp. 12-15, October 1998.
• 13: L. Gwennap. "New processor paradigm: V-IRAM." Microprocessor Report, vol. 12, no. 3, pp. 17-19, March t 998.
• 14: John L. Hennessy , David A. Patterson, Computer architecture (2nd ed.): a quantitative approach, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1996
• 15: Sung I. Hong , Sally A. McKee , Maximo H. Salinas , Robert H. Klenke , James H. Aylor , Wm. A. Wulf, Access Order and Effective Bandwidth for Streams on a Direct Rambus Memory, Proceedings of the 5th International Symposium on High Performance Computer Architecture, p.80, January 09-12, 1999
• 16: IBM. EDO DRAM 4M x 16 Part No. IBMOI65165PT3C. http:llwww. chips.ibm.com/products/memoryl88H2011188H201 t .pdf, 1998.
• 17: IBM. SDRAM IM x 16 x 4 Bank Part No. IBM0364164. http:llwww. chips.ibm.com/products/memoryll 9L3265119L3265,pdf, 1998.
• 18: Kimberly Keeton , David A. Patterson , Yong Qiang He , Roger C. Raphael , Walter E. Baker, Performance characterization of a Quad Pentium Pro SMP using OLTP workloads, Proceedings of the 25th annual international symposium on Computer architecture, p.15-26, June 27-July 02, 1998, Barcelona, Spain
• 19: Christoforos E. Kozyrakis , Stylianos Perissakis , David Patterson , Thomas Anderson , Krste Asanovic , Neal Cardwell , Richard Fromm , Jason Golbus , Benjamin Gribstad , Kimberly Keeton , Randi Thomas , Noah Treuhaft , Katherine Yelick, Scalable Processors in the Billion-Transistor Era: IRAM, Computer, v.30 n.9, p.75-78, September 1997 [doi>10.1109/2.612252]
• 20: David Kroft, Lockup-free instruction fetch/prefetch cache organization, Proceedings of the 8th annual symposium on Computer Architecture, p.81-87, May 12-14, 1981, Minneapolis, Minnesota, United States
• 21: Sally A. McKee , Assaji Aluwihare , Benjamin H. Clark , Robert H. Klenke , Trevor C. Landon , Christopher W. Oliver , Maximo H. Salinas , Adam E. Szymkowiak , Kenneth L. Wright , Wm. A. Wulf , James H. Aylor, Design and evaluation of dynamic access ordering hardware, Proceedings of the 10th international conference on Supercomputing, p.125-132, May 25-28, 1996, Philadelphia, Pennsylvania, United States [doi>10.1145/237578.237594]
• 22: S. A. Mckee , W. A. Wulf, Access ordering and memory-conscious cache utilization, Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture, p.253, January 22-25, 1995
• 23: Basem A. Nayfeh , Lance Hammond , Kunle Olukotun, Evaluation of design alternatives for a multiprocessor microprocessor, Proceedings of the 23rd annual international symposium on Computer architecture, p.67-77, May 22-24, 1996, Philadelphia, Pennsylvania, United States
• 24: B. A. Nayfeh , K. Olukotun , J. P. Singh, The impact of shared-cache clustering in small-scale shared-memory multiprocessors, Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture, p.74, February 03-07, 1996
• 25: Yasuhiro Nunomura , Toru Shimizu , Osamu Tomisawa, M32R/D-Integrating DRAM and Microprocessor, IEEE Micro, v.17 n.6, p.40-48, November 1997 [doi>10.1109/40.641595]
• 26: Steven Przybylski, New DRAM Technologies: A Comprehensive Analysis of the New Architecture, MicroDesign Resources, 1996
• 27: Rambus. "Rambus memory: Enabling technology for PC graphics." Tech. Rep., Rambus Inc., Mountain View CA, October 1994.
• 28: Rambus. "64-megabit Rambus DRAM technology directions." Tech. Rep., Rambus Inc., Mountain View CA, September 1995.
• 29: Rambus. "Comparing RDRAM and SGRAM for 3D applications." Tech. Rep., Ra.mbus Inc., Mountain View CA, October 1996.
• 30: Rambus. "Memory latency comparison." Tech. Rep., Rambus Inc., Mountain View CA, September 1996.
• 31: Rambus. 16/18Mbit & 64/72Mbit Concurrent RDRAM Data Sheet. Rambus, http'Jlwww.rambus.corrddoc,VCnctds.pdf, 1998.
• 32: Rambus. Direct RDRAM 64/72-Mbit Data Sheet. Rambus, http:llwww.rambus.conVdocs/64dDDS.pdf, 1998.
• 33: Parthasarathy Ranganathan , Kourosh Gharachorloo , Sarita V. Adve , Luiz André Barroso, Performance of database workloads on shared-memory systems with out-of-order processors, Proceedings of the eighth international conference on Architectural support for programming languages and operating systems, p.307-318, October 02-07, 1998, San Jose, California, United States
• 34: M. Rosenblum , E. Bugnion , S. A. Herrod , E. Witchel , A. Gupta, The impact of architectural trends on operating system performance, Proceedings of the fifteenth ACM symposium on Operating systems principles, p.285-298, December 03-06, 1995, Copper Mountain, Colorado, United States
• 35: Samsung. FPM DRAM 4M x 16 Part No. KM416V4100C, Samsung Semiconductor, hnp:/lwww.usa.samsungsemi.com/products/prodspec/dramcomp/KM416V40( I)00C.PDF, 1998.
• 36: Ichiro Sase , Nobuyuki Shimizu , Takashi Yoshikawa, Multimedia LSI Accelerator with Embedded DRAM, IEEE Micro, v.17 n.6, p.49-54, November 1997 [doi>10.1109/40.641596]
• 37: Ashley Saulsbury , Fong Pong , Andreas Nowatzyk, Missing the memory wall: the case for processor/memory integration, Proceedings of the 23rd annual international symposium on Computer architecture, p.90-101, May 22-24, 1996, Philadelphia, Pennsylvania, United States
• 38: SLDRAM. 4M x 18 SLDRAM Advance Datasheet. SLDRAM, Inc., hUp :ltwww.sl dram.com/Documents/cotp400b.pdf, 1998.
• 39: R. Wilson. "MoSys tries synthetic SRAM." EE Times Online, July 15, ! 997. http:ltwww.eetimes.com/news/98/1017news/tries.htrnl.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN

General Terms:
Design, Management, Performance