Performance of image and video processing with general-purpose processors and media ISA extensions

ABSTRACT

This paper aims to provide a quantitative understanding of the performance of image and video processing applications on general-purpose processors, without and with media ISA extensions. We use detailed simulation of 12 benchmarks to study the effectiveness of current architectural features and identify future challenges for these workloads.Our results show that conventional techniques in current processors to enhance instruction-level parallelism (ILP) provide a factor of 2.3X to 4.2X performance improvement. The Sun VIS media ISA extensions provide an additional 1.1X to 4.2X performance improvement. The ILP features and media ISA extensions significantly reduce the CPU component of execution time, making 5 of the image processing benchmarks memory-bound.The memory behavior of our benchmarks is characterized by large working sets and streaming data accesses. Increasing the cache size has no impact on 8 of the benchmarks. The remaining benchmarks require relatively large cache sizes (dependent on the display sizes) to exploit data reuse, but derive less than 1.2X performance benefits with the larger caches. Software prefetching provides 1.4X to 2.5X performance improvement in the image processing benchmarks where memory is a significant problem. With the addition of software prefetching, all our benchmarks revert to being compute-bound.

REFERENCES

• 1: Dileep Bhandarkar , Jason Ding, Performance Characterization of the Pentium® Pro Processor, Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture, p.288, February 01-05, 1997
• 2: Ravi Bhargava , Lizy K. John , Brian L. Evans , Ramesh Radhakrishnan, Evaluating MMX technology using DSP and multimedia applications, Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture, p.37-46, November 1998, Dallas, Texas, United States
• 3: Angelos Bilas , Jason Fritts , Jaswinder Pal Singh, Real-Time Parallel MPEG-2 Decoding in Software, Proceedings of the 11th International Symposium on Parallel Processing, p.197-203, April 01-05, 1997
• 4: D. A. CarIson et aI. Multimedia Extensions for a 550MHz RISC Microprocessor. In IEEE Journal of Solid-State Circuits, 1997.
• 5: Thomas M. Conte , Pradeep K. Dubey , Matthew D. Jennings , Ruby B. Lee , Alex Peleg , Salliah Rathnam , Mike Schlansker , Peter Song , Andrew Wolfe, Challenges to Combining General-Purpose and Multimedia Processors, Computer, v.30 n.12, p.33-37, December 1997 [doi>10.1109/2.642799]
• 6: Keith Diefendorff , Pradeep K. Dubey, How Multimedia Workloads Will Change Processor Design, Computer, v.30 n.9, p.43-45, September 1997 [doi>10.1109/2.612247]
• 7: J. Eyre. Assessing General-Purpose Processors for DSP Applications. Berkeley Design Technology Inc. presentation, 1998.
• 8: International Organisation for Standardisation - ISO/IEC JTC I/SC29/WG 11MPEG 98/N2457. MPEG-4 Applications Document, 1998.
• 9: E. Killian. MIPS Extension for Digital Media with 3D. Slides presented at Microprocessor Forum, October 1996.
• 10: L. Kohn , G. Maturana , M. Tremblay , A. Prabhu , G. Zyner, The visual instruction set (VIS) in UltraSPARC, Proceedings of the 40th IEEE Computer Society International Conference, p.462, March 05-09, 1995
• 11: Chunho Lee , Miodrag Potkonjak , William H. Mangione-Smith, MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.330-335, December 01-03, 1997, Research Triangle Park, North Carolina, United States
• 12: Ruby B. Lee, Subword Parallelism with MAX-2, IEEE Micro, v.16 n.4, p.51-59, August 1996 [doi>10.1109/40.526925]
• 13: Ruby B. Lee , Michael D. Smith, Guest Editors' Introduction: Media Processing: A New Design Target, IEEE Micro, v.16 n.4, p.6-9, August 1996 [doi>10.1109/MM.1996.526920]
• 14: Todd Carl Mowry, Tolerating latency through software-controlled data prefetching, Stanford University, Stanford, CA, 1995
• 15: S. Oberman et al. AMD 3DNow! Technology and the K6-2 Microprocessor. In HOTCHIPSIO, 1998.
• 16: V. S. Pai et al. RSIM: A Simulator for Shared-Memory Multiprocessor and Uniprocessor Systems that Exploit ILP. In Proc. 3rd Workshop on Computer Architecture Education, 1997.
• 17: Vijay S. Pai , Parthasarathy Ranganathan , Sarita V. Adve, The Impact of Instruction-Level Parallelism on Multiprocessor Performance and Simulation Methodology, Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture, p.72, February 01-05, 1997
• 18: Alex Peleg , Uri Weiser, MMX Technology Extension to the Intel Architecture, IEEE Micro, v.16 n.4, p.42-50, August 1996 [doi>10.1109/40.526924]
• 19: M. Phillip et al. AltiVec Technology: Accelerating Media Processing Across the Spectrum. In HOTCHIPSIO, Aug 1998.
• 20: Parthasarathy Ranganathan , Vijay S. Pai , Hazim Abdel-Shafi , Sarita V. Adve, The interaction of software prefetching with ILP processors in shared-memory systems, Proceedings of the 24th annual international symposium on Computer architecture, p.144-156, June 01-04, 1997, Denver, Colorado, United States
• 21: Parthasarathy Ranganathan , Kourosh Gharachorloo , Sarita V. Adve , Luiz André Barroso, Performance of database workloads on shared-memory systems with out-of-order processors, Proceedings of the eighth international conference on Architectural support for programming languages and operating systems, p.307-318, October 02-07, 1998, San Jose, California, United States
• 22: D. S. Rice. High-Performance Image Processing Using Special-Purpose CPU Instructions: The UltraSPARC Visual Instruction Set. Master's thesis, Stanford University, 1996.
• 23: Marc Tremblay , J. Michael O'Connor , Venkatesh Narayanan , Liang He, VIS Speeds New Media Processing, IEEE Micro, v.16 n.4, p.10-20, August 1996 [doi>10.1109/40.526921]
• 24: Chia-Lin Yang , Barton Sano , Alvin R. Lebeck, Exploiting instruction level parallelism in geometry processing for three dimensional graphics applications, Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture, p.14-24, November 1998, Dallas, Texas, United States
• 25: Daniel Frederick Zucker, Architecture and arithmetic for multimedia-enhanced processors, Stanford University, Stanford, CA, 1998
• 26: Daniel F. Zucker , Ruby B. Lee , Michael J. Flynn, An Automated Method for Software Controlled Cache Prefetching, Proceedings of the Thirty-First Annual Hawaii International Conference on System Sciences-Volume 7, p.106, January 06-09, 1998 [doi>10.1109/HICSS.1998.649189]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.1 CONTROL STRUCTURES AND MICROPROGRAMMING

Additional Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES

  I. Computing Methodologies
  I.6 SIMULATION AND MODELING

General Terms:
Design, Experimentation, Performance, Theory