Getting to the bottom of deep submicron II

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Getting to the bottom of deep submicron II: a global wiring paradigm

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International Symposium on Physical Design archive
Proceedings of the 1999 international symposium on Physical design table of contents

Monterey, California, United States

Pages: 193 - 200

Year of Publication: 1999

ISBN:1-58113-089-9

Authors

Dennis Sylvester	University of California, Berkeley, Department of Electrical Engineering and Computer Sciences
Kurt Keutzer	University of California, Berkeley, Department of Electrical Engineering and Computer Sciences

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 12, Downloads (12 Months): 41, Citation Count: 24

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Dennis Sylvester , Kurt Keutzer, Getting to the bottom of deep submicron, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.203-211, November 08-12, 1998, San Jose, California, United States [doi>10.1145/288548.288614]
	2	National Technology Roadmap for Semiconductors, Semiconductor Industry Association, 1997.
	3	M. Bohr et al., "A High Performance 0.25 ttm Logic Technology Optimized for 1.SV Operation," Proc. oflEDM, pp. 847-50, 1996.
	4	Ralph H. J. M. Otten, Global wires: harmful?, Proceedings of the 1998 international symposium on Physical design, p.104-109, April 06-08, 1998, Monterey, California, United States [doi>10.1145/274535.274550]
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	8	P. Zarkesh-Ha and J.D. Meindl, "Stochastic net length distributions for global interconnects in a heterogeneous system-on-achip," Proc. of VLSI Symposium on Tech., pp. 44--5, 1998.
	9	D. Sylvester, C. Hu, O.S. Nakagawa, and S.Y. Oh, "interconnect Scaling: Signal Integrity and Performance in Future High-Speed CMOS Designs," Proc. of VLSI Symposium on Tech., pp. 42-3, 1998.
	10	W.E. Donath, "Placement and average interconnection lengths of computer logic," IEEE Trans. on Circuits and Systems, v. 26, pp. 272- 277, Apr. 1979.
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	13	Yehia Massoud , Steve Majors , Tareq Bustami , Jacob White, Layout techniques for minimizing on-chip interconnect self inductance, Proceedings of the 35th annual conference on Design automation, p.566-571, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277194]
	14	http://www-device.eecs.berkeley.edu/~dennis/BACPAC
	15	T. Sakurai, "Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSrs," IEEE Trans. on Electron Devices, v. 40, pp. 118-124, Jan. 1993.
	16	Q. Zhn and S. Tam, "Package Clock Distribution Design Optimization for High-Speed and Low-Power VLSI's," IEEE Trans. Comp, Pack, and Manuf Tech., v. 20, pp. 56-63, Feb. 1997.
	17	R.R. Tummala and E. Rymaszewski, Microelecrronics Packaging Handbook, Van Nostrand Reinhold, New York, 1989.
	18	O.S. Nakagawa, D. Sylvester, J.G. McBride, and S-Y. Oh, "Closed-form modeling of on-chip crosstalk noise in deep submicron ULSI interconnect," lip Journal, pp. 39-45, Aug 1998.
	19	W.S. Song and L.A. Glasser, "Power Distribution Techniques for VLSI Circuits," IEEE Journal of Solid-State Circuits, v. 21, pp. 150- 156, Feb. 1986.

CITED BY 24

	I-Min Liu , Adnan Aziz , D. F. Wong, Meeting delay constraints in DSM by minimal repeater insertion, Proceedings of the conference on Design, automation and test in Europe, p.436-440, March 27-30, 2000, Paris, France
	M. Graziano , M. Delaurenti , M. Zamboni, Power supply design parameters prediction for high performance IC design flows, Proceedings of the 2000 international workshop on System-level interconnect prediction, p.61-67, April 08-09, 2000, San Diego, California, United States
	Ankireddy Nalamalpu , Wayne Burleson, Boosters for driving long on-chip interconnects: design issues, interconnect synthesis and comparison with repeaters, Proceedings of the 2001 international symposium on Physical design, p.204-211, April 01-04, 2001, Sonoma, California, United States
	M. Graziano , G. Masera , G. Piccinini , M. Zamboni, Hierarchical power supply noise evaluation for early power grid design prediction, Proceedings of the 2001 international workshop on System-level interconnect prediction, p.183-188, March 31-April 01, 2001, Sonoma, California, United States
	Prashant Saxena , Noel Menezes , Pasquale Cocchini , Desmond A. Kirkpatrick, The scaling challenge: can correct-by-construction design help?, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA
	Dennis Sylvester , Himanshu Kaul, Future performance challenges in nanometer design, Proceedings of the 38th conference on Design automation, p.3-8, June 2001, Las Vegas, Nevada, United States
	Robert K. Brayton, The future of logic synthesis and verification, Logic Synthesis and Verification, Kluwer Academic Publishers, Norwell, MA, 2001
	Atul Maheshwari , Wayne Burleson, Repeater and current-sensing hybrid circuits for on-chip interconnects, Proceedings of the 13th ACM Great Lakes symposium on VLSI, April 28-29, 2003, Washington, D. C., USA
	Axel Jantsch , Hannu Tenhunen, Will networks on chip close the productivity gap?, Networks on chip, Kluwer Academic Publishers, Hingham, MA, 2003
	Vishak Venkatraman , Andrew Laffely , Jinwook Jang , Hempraveen Kukkamalla , Zhi Zhu , Wayne Burleson, NoCIC: a spice-based interconnect planning tool emphasizing aggressive on-chip interconnect circuit methods, Proceedings of the 2004 international workshop on System level interconnect prediction, February 14-15, 2004, Paris, France
	Dinesh Pamunuwa , Li-Rong Zheng , Hannu Tenhunen, Maximizing throughput over parallel wire structures in the deep submicrometer regime, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.2, p.224-243, April 2003
	Vishak Venkatraman , Atul Maheshwari , Wayne Burleson, Mitigating static power in current-sensed interconnects, Proceedings of the 14th ACM Great Lakes symposium on VLSI, April 26-28, 2004, Boston, MA, USA
	Prashant Saxena, The scaling of interconnect buffer needs, Proceedings of the international workshop on System-level interconnect prediction, March 04-05, 2006, Munich, Germany
	Rahul Rao , Kanak Agarwal , Dennis Sylvester , Richard Brown , Kevin Nowka , Sani Nassif, Approaches to run-time and standby mode leakage reduction in global buses, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
	Dennis Sylvester , Kurt Keutzer, Rethinking Deep-Submicron Circuit Design, Computer, v.32 n.11, p.25-33, November 1999
	M. Graziano , G. Masera , G. Piccinini , M. Zamboni, Power Supply Design Parameters for Switching-Noise Control in Deep-Submicron Circuits Design Flows, Analog Integrated Circuits and Signal Processing, v.31 n.3, p.225-248, June 2002
	Bradford M. Beckmann , David A. Wood, Managing Wire Delay in Large Chip-Multiprocessor Caches, Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, p.319-330, December 04-08, 2004, Portland, Oregon
	Qingli Zhang , Jinxiang Wang , Yizheng Ye, An energy-efficient temporal encoding circuit technique for on-chip high performance buses, Proceedings of the 16th ACM Great Lakes symposium on VLSI, April 30-May 01, 2006, Philadelphia, PA, USA
	M. P. Flynn , J. J. Kang, Global signaling over lossy transmission lines, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.985-992, November 06-10, 2005, San Jose, CA
	Himanshu Kaul , Dennis Sylvester , David Blaauw , Trevor Mudge , Todd Austin, DVS for On-Chip Bus Designs Based on Timing Error Correction, Proceedings of the conference on Design, Automation and Test in Europe, p.80-85, March 07-11, 2005
	Bradford M. Beckmann , David A. Wood, TLC: Transmission Line Caches, Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture, p.43, December 03-05, 2003
	Prashant Singh , Jae-sun Seo , David Blaauw , Dennis Sylvester, Self-timed regenerators for high-speed and low-power on-chip global interconnect, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.16 n.6, p.673-677, June 2008
	Daniele Ludovici , Georgi Nedeltchev Gaydadjiev , Davide Bertozzi , Luca Benini, Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip, Proceedings of the 19th ACM Great Lakes symposium on VLSI, May 10-12, 2009, Boston Area, MA, USA
	Jae-sun Seo , Igor L. Markov , Dennis Sylvester , David Blaauw, On the decreasing significance of large standard cells in technology mapping, Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, November 10-13, 2008, San Jose, California