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A method of measuring nets routability for MCM's general area routing problems
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Source International Symposium on Physical Design archive
Proceedings of the 1999 international symposium on Physical design table of contents
Monterey, California, United States
Pages: 186 - 192  
Year of Publication: 1999
ISBN:1-58113-089-9
Authors
Kusnadi  Dept. of Electrical and Computer Engineering, The University of Arizona, Tucson, Arisona
Jo Dale Carothers  Dept. of Electrical and Computer Engineering, The University of Arizona, Tucson, Arisona
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 4,   Downloads (12 Months): 11,   Citation Count: 8
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
S. D. Brown, J. Rose, Z. G. Vranesic, "A Stochastic Model to Predict the Routability of Field-Programmable Gate Arrays," IEEB Trans. on Computer.Aided Design of Integrated Circuits and Systems, Vol. 12, No. 12, pp. 1827-1838, Dec. 1993.
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A. A. EI-Gamal, "Two-dimensional Stochastic Model for Interconnections in Master Slice integrated Circuits," IEEE Trans. on Circuits and Systems, vol. CAS-28, pp. 127-138, Feb. 1981.
 
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7
W. R. Heller, C. G. Hsi, W. F. Mikhail, "Wireability - Designing Wiring Space for Chips and Chip P~es," IBEB Design and Teat, pp. 43-51, Aug. 1984.
 
8
N. Iso, Y. Kawaguchi, T. Hirata, "Efficient Routability Checking for Global Wires in Planar Layouts," IE- ICE 23,ann. on b'hndamentals of Electronics, Communications and Computer Sciences, vol. ES0-A, no. 10, pp. 1878-1882, Oct. 1997.
 
9
J. Jaja, S. A. Wu, "On routing Two-Terminal Nets in the Presence of Obstacles," IEEE Trans. on Computer- Aided Design, Vol. 8, No. 5, pp. 563-570, May 1989.
 
10
K. Y. Khoo, J, Cong, "An Efficient Multilayer MCM Router Based on Four-Via Routing," IEEE 23,ann. on Computer-aided Design of Integrated Circuits and Systems, vol. 14, no. 10, pp. 1277-1290, Oct. 1995.
 
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12
F. M. Maley, "Testing Homotopic Routability Under Polygonal Wiring Rules," Aigorithmica, Vol. 15, pp. 1-16, 1996.
 
13
M. Pecht, Y. T. Wong, Advanced Routing of Electronic Modules, Boca Raton, CRC Press, 1996.
 
14
S. Sastry, A. C. Parker, "Stochastic Models for Wireability Analysis of Gate Arrays," IEEE Trans. on Computer-aided Design, vol, CAD-5, pp. 53-65, Jan. 1986.
 
15
I. E. Shuterland, D. Oestreicher, "How Big Should a Printed Circuit Board Be?," IEEE Trans. on Computer, vol C-22, pp. 537-543, May 1973.
 
16
D. C. Wang, "Method for Estimating Routability and Congestion in A Cell Placement for Integrated Circuit Chip," United States Patent 5,587,923, 1996.

CITED BY  8

Collaborative Colleagues:
Kusnadi: colleagues
Jo Dale Carothers: colleagues