Standard cell placement for even on-chip thermal distribution

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Standard cell placement for even on-chip thermal distribution

Full text

Pdf (724 KB)

Source

International Symposium on Physical Design archive
Proceedings of the 1999 international symposium on Physical design table of contents

Monterey, California, United States

Pages: 179 - 184

Year of Publication: 1999

ISBN:1-58113-089-9

Authors

Ching-Han Tsai	Department of Electrical and Computer Engineering, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign
Sung-Mo (Steve) Kang	Department of Electrical and Computer Engineering, Coordinated Science Laboratory, University of Illinois at Urbana-Champaign

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 14, Downloads (12 Months): 33, Citation Count: 9

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/299996.300067 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	M. N. Ozisik, Douauv~y v~ue r~om~ii,.~ o~ rse~ ~oudition," New York NY:Dover, 1908.
	2	M. Huang, F. Romeo, and A. Sangiovani-Vincentell "An efficient general cooling schedule for simulated annealing," Proc. Int. Con/. Computer-Aided Design, pp. 381-384, Nov. 1986.
	3	M. D. Osterman and M. Pecht, "Component Placemeat for Reliability on Conductively Cooled Printed Wiring Boards," ASME J. of Packaging, 111(3):149-
	4	R. Darveaux, I. Turlik, L. T. Hwang, and A. Reisman, "Thermal Stress Analysis of a Multichip Package Design," IEEE ~ns. Comp. , Hybrids, Manufaet. Technol., pp. 663-672, Dec. 1989.
	5	M. D. Osterman and M. Pecht, "Placement for Reliability and Routability of Convectively Cooled PWBs," IEEE Trans. on CAD, 9(7):734-744, Jul. 1990.
	6	N. K. Verghese and D. J. Allstot, "Rapid Simulation of substrate coupling effects in mixed-mode IC's," Proc. IEEECustom Integrated Circuits Conf., pp. 18.3.1- 18.3.4, 1993.
	7	B. R. Stanisic, N. K. Verghese, R. A. Rutenbar, L. R. Carley and D. J. Allstot, "Addressing Substrate Coupling in Mixed-Mode IC's: Simulation and Power Tempe~ture values for ~ruct Temperature valuta for strud Distribution Synthesis," IEEE J. of Solid-State Circuits, vol. 29, no. 3, pp. 226-237, M~. 1994.
	8	S. Mitra, R. A. Rutenbar, L. R. Carley and D. J. A!lstot, "Substrate-Aware Mixed-Signal Macrocell Placement in WB2GHT," IEEE J. of Solid.State Circuits, vol. 30, no. 3, pp. 269-278, Mar. 1995.
	9	Kai-Yuan Chao , D. F. Wong, Thermal placement for high-performance multichip modules, Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors, p.218-223, October 02-04, 1995
	10	I. L. Wemple and A. T. Yang, "Integrated Circuit Substrate Coupling Models Based on Voronoi Tessellation," IEEE 2~'ans. on CAD, 14(12):1459--1469, Dec. 1995.
	11	Yi-Kan Cheng , Chin-Chi Teng , Abhijit Dharchoudhury , Elyse Rosenbaum , Sung-Mo Kang, ICET: a complete chip-level thermal reliability diagnosis tool for CMOS VLSI chips, Proceedings of the 33rd annual conference on Design automation, p.548-551, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240622]
	12	Chris C. N. Chu , D. F. Wong, A matrix synthesis approach to thermal placement, Proceedings of the 1997 international symposium on Physical design, p.163-168, April 14-16, 1997, Napa Valley, California, United States [doi>10.1145/267665.267708]
	13	Y. K. Cheng, P. Raha, C. C. Teng, E. Rosenbaum, and S.-M. Kang, "ILLIADS-T: An Electrothermal Timing Simulator for Temperature-Sensitive Reliability Diagnosis of CMOS VLSI Chips," IEEE Trans. on CAD, Vol. 17, No. 8, pp. 668-681, Aug. 1998.
	14	Hans Eisenmann , Frank M. Johannes, Generic global placement and floorplanning, Proceedings of the 35th annual conference on Design automation, p.269-274, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277119]

CITED BY 9

	Shamik Das , Anantha Chandrakasan , Rafael Reif, Timing, energy, and thermal performance of three-dimensional integrated circuits, Proceedings of the 14th ACM Great Lakes symposium on VLSI, April 26-28, 2004, Boston, MA, USA
	Aditya Bansal , Mesut Meterelliyoz , Siddharth Singh , Jung Hwan Choi , Jayathi Murthy , Kaushik Roy, Compact thermal models for estimation of temperature-dependent power/performance in FinFET technology, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Rajarshi Mukherjee , Seda Ogrenci Memik , Gokhan Memik, Temperature-aware resource allocation and binding in high-level synthesis, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Rajarshi Mukherjee , Seda Ogrenci Memik , Gokhan Memik, Peak temperature control and leakage reduction during binding in high level synthesis, Proceedings of the 2005 international symposium on Low power electronics and design, August 08-10, 2005, San Diego, CA, USA
	Pilok Lim , Taewhan Kim, Thermal-aware high-level synthesis based on network flow method, Proceedings of the 4th international conference on Hardware/software codesign and system synthesis, October 22-25, 2006, Seoul, Korea
	Hushrav D. Mogal , Kia Bazargan, Microarchitecture floorplanning for sub-threshold leakage reduction, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
	Rajarshi Mukherjee , Seda Ogrenci Memik, An integrated approach to thermal management in high-level synthesis, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.14 n.11, p.1165-1174, November 2006
	Xin Li , Yuchun Ma , Xianlong Hong, A novel thermal optimization flow using incremental floorplanning for 3D ICs, Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, January 19-22, 2009, Yokohama, Japan
	Hushrav D Mogal , Kia Bazargan, Thermal-aware floorplanning for task migration enabled active sub-threshold leakage reduction, Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, November 10-13, 2008, San Jose, California