Partitioning with terminals

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Partitioning with terminals: a “new” problem and new benchmarks

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International Symposium on Physical Design archive
Proceedings of the 1999 international symposium on Physical design table of contents

Monterey, California, United States

Pages: 151 - 157

Year of Publication: 1999

ISBN:1-58113-089-9

Authors

C. J. Alpert	IBM Austin Research Laboratory, Austin, TX
A. E. Caldwell	UCLA Computer Science Dept., Los Angeles, CA
A. B. Kahng	UCLA Computer Science Dept., Los Angeles, CA
I. L. Markov	UCLA Computer Science Dept., Los Angeles, CA

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 6, Downloads (12 Months): 14, Citation Count: 1

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	C. J. Alpert, "Partitioning Benchmarks for VLSI CAD Community", Web page, http: //vlsicad. cs.ucla, edu/ -cheese/benchmarks. html
	2	Charles J. Alpert, The ISPD98 circuit benchmark suite, Proceedings of the 1998 international symposium on Physical design, p.80-85, April 06-08, 1998, Monterey, California, United States [doi>10.1145/274535.274546]
	3	Charles J. Alpert , Jen-Hsin Huang , Andrew B. Kahng, Multilevel circuit partitioning, Proceedings of the 34th annual conference on Design automation, p.530-533, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266275]
	4	Charles J. Alpert , Andrew B. Kahng, Recent directions in netlist partitioning: a survey, Integration, the VLSI Journal, v.19 n.1-2, p.1-81, Aug. 1995 [doi>10.1016/0167-9260(95)00008-4]
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	13	George Karypis , Rajat Aggarwal , Vipin Kumar , Shashi Shekhar, Multilevel hypergraph partitioning: application in VLSI domain, Proceedings of the 34th annual conference on Design automation, p.526-529, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266273]
	14	G. Karypis, R. Aggarwal, V. Kumar and S. Shekhar, "Multilevel Hypergraph Partitioning: Applications in VLSI Domain", technical report, University of Minnesota Computer Science Department, March 27, 1998.
	15	B. Landman and R. Russo, "On a Pin Versus Block Relationship for Partitioning of Logic Graphs", IEEE Transactions on Computers C- 20(12) (1971), pp. 1469-1479.
	16	P. R. Suaris and G. Kedem, "Quadrisection: A New Approach to Standard Cell Layout", Proc. IEEE/ACM International Conference on Computer-Aided Design, 1987, pp. 474-477.
	17	Dennis Sylvester , Kurt Keutzer, Getting to the bottom of deep submicron, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.203-211, November 08-12, 1998, San Jose, California, United States [doi>10.1145/288548.288614]