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On the behavior of congestion minimization during placement
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Source International Symposium on Physical Design archive
Proceedings of the 1999 international symposium on Physical design table of contents
Monterey, California, United States
Pages: 145 - 150  
Year of Publication: 1999
ISBN:1-58113-089-9
Authors
Maogang Wang  Department of Electrical and Computer Engineering, Northwestern University, Evanston, IL
Majid Sarrafzadeh  Department of Electrical and Computer Engineering, Northwestern University, Evanston, IL
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 2,   Downloads (12 Months): 19,   Citation Count: 30
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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J. M. Kleinhans, G. Sigl, F. M. Johannes, and K. J. Antreich. "GORDIAN: VLSI Placement by Quadratic Programming and Slicing Optimization". IEEE Trans. actions on Computer Aided Design, 10(3):365-365, 1991.
 
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S. Mayrhofer and U. Lauther. "Congestion-Driven Placement Using a New Multi-Partitioning Heuristic". in International Conference on Computer-Aided Design, pages 332-335. IEEE/ACM, November 1990.
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Y. Saab. "A Fast Clustering-based Min-cut Placement Algorithm with Simulated-annealing Performance". VLSI Design: An International Journal o.f Custom- Chip Design, Simulation, and Testing, 5(1):37-48, 1996.
 
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C. Sechen. VLSI Placement and Global Routing Using Simulated Annealing. Kluwer, B. V., Deventer, The Netherlands, 1988.
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CITED BY  30

Collaborative Colleagues:
Maogang Wang: colleagues
Majid Sarrafzadeh: colleagues