| Simultaneous buffer insertion and non-Hanan optimization for VLSI interconnect under a higher order AWE model |
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International Symposium on Physical Design
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Proceedings of the 1999 international symposium on Physical design
table of contents
Monterey, California, United States
Pages: 133 - 138
Year of Publication: 1999
ISBN:1-58113-089-9
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Authors
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Jiang Hu
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Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN
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Sachin S. Sapatnekar
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Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN
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Downloads (6 Weeks): 1, Downloads (12 Months): 9, Citation Count: 3
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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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H. Hou, J. Hu and S. S. Sapatnekar, "NonHanan routing", to be published on IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
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L. P. V. Ginneken, "Buffer placement in distributed RC-tree networks for minimal Elmore delay", Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 865-868, 1990.
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Y. Jiang, S. S. Sapatnekar, C. Bamji and J. Kim, "Combined transistor sizing with buffer insertion for timing optimization", Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 605-608, 1998.
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