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Gate sizing with controlled displacement
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Source International Symposium on Physical Design archive
Proceedings of the 1999 international symposium on Physical design table of contents
Monterey, California, United States
Pages: 127 - 132  
Year of Publication: 1999
ISBN:1-58113-089-9
Authors
Wei Chen  Department of Electrical Engineering - System, University of Southern California, Los Angeles, CA
Cheng-Ta Hsieh  Department of Electrical Engineering - System, University of Southern California, Los Angeles, CA
Massoud Pedram  Department of Electrical Engineering - System, University of Southern California, Los Angeles, CA
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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B.M. Riess, G.G. Ettelt, "SPEED: Fast and Efficient Timing Driven Placement", Proc. Intl. Symposium Of Circuits and Systems, pp.377- 380, 1995.
 
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M. Berkelaar, "Area-Power-Delay Trade-off in Logic Synthesis~, Ph.D Thesis, Eindhoven University of Technology, 1992.
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Collaborative Colleagues:
Wei Chen: colleagues
Cheng-Ta Hsieh: colleagues
Massoud Pedram: colleagues