Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesis

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Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesis

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International Symposium on Physical Design archive
Proceedings of the 1999 international symposium on Physical design table of contents

Monterey, California, United States

Pages: 74 - 81

Year of Publication: 1999

ISBN:1-58113-089-9

Authors

Michael A. Riepe	University of Michigan, Ann Arbor, MI
Karem A. Sakallah	University of Michigan, Ann Arbor, MI

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 9, Downloads (12 Months): 25, Citation Count: 3

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 3

	Michael A. Riepe , Karem A. Sakallah, Transistor placement for noncomplementary digital VLSI cell synthesis, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.8 n.1, p.81-107, January 2003
	L. Macchiarulo , L. Benini , E. Macii, On-the-fly layout generation for PTL macrocells, Proceedings of the conference on Design, automation and test in Europe, p.546-551, March 2001, Munich, Germany
	Tatjana Serdar , Carl Sechen, AKORD: transistor level and mixed transistor/gate level placement tool for digital data paths, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.91-97, November 07-11, 1999, San Jose, California, United States