Interconnect coupling noise in CMOS VLSI circuits

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Interconnect coupling noise in CMOS VLSI circuits

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International Symposium on Physical Design archive
Proceedings of the 1999 international symposium on Physical design table of contents

Monterey, California, United States

Pages: 48 - 53

Year of Publication: 1999

ISBN:1-58113-089-9

Authors

Kevin T. Tang	Department of Electrical and Computer Engineering, University of Rochester, Rochester, New York
Eby G. Friedman	Department of Electrical and Computer Engineering, University of Rochester, Rochester, New York

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 7, Downloads (12 Months): 42, Citation Count: 10

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	11	A. R. Djordjevi<~, T. K. Sarkar, and R. F. Haxrington, "Time- Domain Response of Multiconductor Transmission Lines,~ Proceedings of the IEEE, Vol. 75, No. 6, pp. 743-764, June 1987.
	12	T. V. Dish, B. Cabon, and j. Chilo, "SPICE Simulation of Lossy and Coupled Interconneetion Lines," IEEE Transactions on Components, Packaging, and Manufacturing Technology-Part B, Vol. 17, No. 2, pp. 134-146, May 1994.
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CITED BY 10

	Liang Yin , Lei He, An efficient analytical model of coupled on-chip RLC interconnects, Proceedings of the 2001 conference on Asia South Pacific design automation, p.385-390, January 2001, Yokohama, Japan
	Jun Chen , Lei He, A decoupling method for analysis of coupled RLC interconnects, Proceedings of the 12th ACM Great Lakes symposium on VLSI, April 18-19, 2002, New York, New York, USA
	Jason Cong , Majid Sarrafzadeh, Incremental physical design, Proceedings of the 2000 international symposium on Physical design, p.84-92, May 2000, San Diego, California, United States
	Kevin T. Tang , Eby G. Friedman, Noise estimation due to signal activity for capacitively coupled CMOS logic gates, Proceedings of the 10th Great Lakes symposium on VLSI, p.171-176, March 02-04, 2000, Chicago, Illinois, United States
	Atul Maheshwari , Wayne Burleson, Repeater and current-sensing hybrid circuits for on-chip interconnects, Proceedings of the 13th ACM Great Lakes symposium on VLSI, April 28-29, 2003, Washington, D. C., USA
	Kanak Agarwal , Dennis Sylvester , David Blaauw, A simplified transmission-line based crosstalk noise model for on-chip RLC wiring, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.858-864, January 27-30, 2004, Yokohama, Japan
	Kevin T. Tang , Eby G. Friedman, The Effect of Signal Activity on Propagation Delay of CMOS Logic Gates Driving Coupled On-Chip Interconnections, Analog Integrated Circuits and Signal Processing, v.31 n.3, p.209-224, June 2002
	Narender Hanchate , Nagarajan Ranganathan, A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.11 n.3, p.711-739, July 2006
	Dimitrios Velenis , Marios C. Papaefthymiou , Eby G. Friedman, Reduced Delay Uncertainty in High Performance Clock Distribution Networks, Proceedings of the conference on Design, Automation and Test in Europe, p.10068, March 03-07, 2003
	Jingye Xu , Abinash Roy , Masud H. Chowdhury, Noise separation in analog integrated circuits using independent component analysis technique, Integrated Computer-Aided Engineering, v.15 n.2, p.163-180, April 2008