| Incremental capacitance extraction and its application to iterative timing-driven detailed routing |
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International Symposium on Physical Design
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Proceedings of the 1999 international symposium on Physical design
table of contents
Monterey, California, United States
Pages: 42 - 47
Year of Publication: 1999
ISBN:1-58113-089-9
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Authors
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Yanhong Yuan
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Center for Parallel and Distributed Computing, Department of Electrical and Computer Engineering, Northwestern University, Evanston, IL
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Prithviraj Banerjee
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Center for Parallel and Distributed Computing, Department of Electrical and Computer Engineering, Northwestern University, Evanston, IL
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Downloads (6 Weeks): 2, Downloads (12 Months): 9, Citation Count: 0
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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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K.Zhu and D.F.Wong, "Switch Bound Allocation for Maximizing Routability in Timing Driven Routing of FPGA's," IEEETrans. CAD, 1998, pp316-323.
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K. Nabors and J. White, "FASTCAP: A Multipole- Accelerated 3-D Capacitance Extraction Program;' IEEE Trans. CAD, pp. 1447-1459, Nov. 1991.
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