Buffer insertion for clock delay and skew minimization

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Buffer insertion for clock delay and skew minimization

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International Symposium on Physical Design archive
Proceedings of the 1999 international symposium on Physical design table of contents

Monterey, California, United States

Pages: 36 - 41

Year of Publication: 1999

ISBN:1-58113-089-9

Authors

X. Zeng	Department of Electrical and Computer Engineering, University of North Carolina at Charlotte, NC and Department of Electronic Engineering, Fudan University, Shanghai 200433, China
D. Zhou	Department of Electrical and Computer Engineering, University of North Carolina at Charlotte, NC
Wei Li	Department of Electrical and Computer Engineering, University of North Carolina at Charlotte, NC

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 12, Downloads (12 Months): 59, Citation Count: 4

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Michael A. B. Jackson , Arvind Srinivasan , E. S. Kuh, Clock routing for high-performance ICs, Proceedings of the 27th ACM/IEEE conference on Design automation, p.573-579, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123406]
	2	Andrew Kahng , Jason Cong , Gabriel Robins, High-performance clock routing based on recursive geometric matching, Proceedings of the 28th conference on ACM/IEEE design automation, p.322-327, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127688]
	3	B. Wu and N. Sherwani. "Effective Buffer insertion of Clock Tree for High-Speed VLSI Circuits". Microelectronics Journal, 23:291-300, July 1992.
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	5	John Lillis , Chung-Kuan Cheng , Ting-Ting Y. Lin, Optimal wire sizing and buffer insertion for low power and a generalized delay model, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.138-143, November 05-09, 1995, San Jose, California, United States
	6	S. Pullela, N. Menezes, J. Omar and L. Pillage, "Skew and Delay Optimization for Reliable Buffered Clock Trees", Proc. IEEE Int. Conf. on Computer-Aided Design, pp. 556-562,1993.
	7	L.P.P.P. van Ginneken. "Buffer placement in distributed RC- tree networks for minimal Elmore delay". International Symposium on Circuits and Systems, pp. 865-868, 1990.
	8	Y. P. Chen and D.F. Wong, "An algorithm for zero-skew clock tree muting with buffer insertion", Proc. European on Computer- Aided Design, pp.219-223, 1994.
	9	Jason Cong , Lei He , Cheng-Kok Koh , Patrick H. Madden, Performance optimization of VLSI interconnect layout, Integration, the VLSI Journal, v.21 n.1-2, p.1-94, Nov. 1996 [doi>10.1016/S0167-9260(96)00008-9]
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	11	F. Anceau, "A synchronous approach for clocking VI~I systerns", IEEE Y. Solid-State Circuits, vol. SC-I 7, pp. 51-56, 1982.
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	14	S. Dhar and M.A. Fmnklin~ "Optimum Buffer Circuits for Driving Long Uniform Lines", lEEK J. of Solid-State Circuits, vol. 26(no.1), pp.32-40, Jan. 1991.
	15	H. Kim and D. Zhou, "An Automatic Clock Tree Design System for High-Speed VLSI Designs: planar clock routing with the treatment of obstacles", International Symposium on Circuits and Systems, 1999 to appear.
	16	D. Zhou, W. Li and X. Zeng, "An Effective Buffer Insertion Algorithm for High-Speed Clock Network", submitted to IEEE Design Automation Conference, 1999.
	17	D. Zhou and X.Y. Liu, "On the Optimal Drivers of High- Speed Low Power ICs", International Journal of High Speed Electronics and Systems, vol. 7(no.2), pp. 287-303, 1996.

CITED BY 4

	Jatuchai Pangjun , Sachin S. Sapatnekar, Low-power clock distribution using multiple voltages and reduced swings, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.3, p.309-318, June 2002
	Xinjie Wei , Yici Cai , Meng Zhao , Xianlong Hong, Legitimate Skew Clock Routing with Buffer Insertion, Journal of VLSI Signal Processing Systems, v.42 n.2, p.107-116, February 2006
	Yanfeng Wang , Qiang Zhou , Yici Cai , Jiang Hu , Xianlong Hong , Jinian Bian, Low power clock buffer planning methodology in F-D placement for large scale circuit design, Proceedings of the 2008 conference on Asia and South Pacific design automation, January 21-24, 2008, Seoul, Korea
	Yun Yang , Shinji Kimura, The Optimal Architecture Design of Two-Dimension Matrix Multiplication Jumping Systolic Array, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, v.E91-A n.4, p.1101-1111, April 2008