Post-routing timing optimization with routing characterization

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Post-routing timing optimization with routing characterization

Full text

Pdf (576 KB)

Source

International Symposium on Physical Design archive
Proceedings of the 1999 international symposium on Physical design table of contents

Monterey, California, United States

Pages: 30 - 35

Year of Publication: 1999

ISBN:1-58113-089-9

Authors

Chieh Changfan	Computer Science Dept. University of California, Riverside and Avant! Corporation, 46871 Bayside Parkway, Fremont, CA
Yu-Chin Hsu	Avant! Corporation, 46871 Bayside Parkway, Fremont, CA
Fur-Shing Tsai	Avant! Corporation, 46871 Bayside Parkway, Fremont, CA

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 12, Citation Count: 0

Additional Information:

references index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/299996.300013 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Hsiao-Pin Su , Allen C.-H. Wu , Youn-Long Lin, Performance-driven soft-macro clustering and placement by preserving HDL design hierarchy, Proceedings of the 1998 international symposium on Physical design, p.12-17, April 06-08, 1998, Monterey, California, United States [doi>10.1145/274535.274537]
	2	Amir H. Salek , Jinan Lou , Massoud Pedram, A DSM design flow: putting floorplanning, technology-mapping, and gate-placement together, Proceedings of the 35th annual conference on Design automation, p.128-134, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277072]
	3	Ralph H. J. M. Otten , Robert K. Brayton, Planning for performance, Proceedings of the 35th annual conference on Design automation, p.122-127, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277071]
	4	M. T-C. Lee, T-Y. Liu, K. F-S. Tsai, E. S-Z. Lin, and Y. C. Hsu, "Incremental Timing Optimization for Physical Design by Interacting Logic Restructuring and Layout," International Workshop on Logic Synthesis, June, 1998.
	5	T. Sakurai and K. Tamaru, "Simple formulas for two and three dimensional capacitance," IEEE ~ans. Electronic Devices, 1993'
	6	Hai Zhou , D. F. Wong, Global routing with crosstalk constraints, Proceedings of the 35th annual conference on Design automation, p.374-377, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277147]
	7	C. Chiang, M. Sarrafzadeh, and C.K. Wong, "A powerful global router: Based on Steiner min-max tree." Proc DA C 1989, pp.2-5.
	8	Jin-fuw Lee , Donald T. Tang, An algorithm for incremental timing analysis, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.696-701, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217613]
	9	K.J. Singh, A.R. Wang, R.K. Brayton, and A.Sangiovanni-Vincentelli, "Timing Optimization of Combinational Logic," Proc ICCAD 1988, pp282-285.
	10	Richard L. Rudell , Alberto Sangiovanni-Vincentelli, Logic synthesis for vlsi design, 1989