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EMI-noise analysis under ASIC design environment
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Source International Symposium on Physical Design archive
Proceedings of the 1999 international symposium on Physical design table of contents
Monterey, California, United States
Pages: 16 - 21  
Year of Publication: 1999
ISBN:1-58113-089-9
Authors
Sachio Hayashi  DA Development Dept., Semiconductor DA & Test Engineering Center, Toshiba Corporation
Masaaki Yamada  DA Development Dept., Semiconductor DA & Test Engineering Center, Toshiba Corporation
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 8,   Downloads (12 Months): 26,   Citation Count: 1
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Derrick Duehren et al., "l/O-buffer modeling spec simplifies simulation for high-speed systems", EDN Mar 16, 1995, pp.65-68.
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Howard H. Chert et al., "Interconnect and Circuit Modeling Techniques for Full-Chip Power Supply Noise Analysis", IEEE Trans. Comp., Packag., Manufact., Technol., vol.21, pp.209-215, Aug. 1998.
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Collaborative Colleagues:
Sachio Hayashi: colleagues
Masaaki Yamada: colleagues