A methodology to analyze power, voltage drop and their effects on clock skew/delay in early stages of design

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A methodology to analyze power, voltage drop and their effects on clock skew/delay in early stages of design

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International Symposium on Physical Design archive
Proceedings of the 1999 international symposium on Physical design table of contents

Monterey, California, United States

Pages: 9 - 15

Year of Publication: 1999

ISBN:1-58113-089-9

Authors

Masato Iwabuchi	Hitachi, Ltd., 6-16-3 Shinmachi, Ome, Tokyo 198-8512, Japan
Noboru Sakamoto	Hitachi, Ltd., 6-16-3 Shinmachi, Ome, Tokyo 198-8512, Japan
Yasushi Sekine	Hitachi, Ltd., 6-16-3 Shinmachi, Ome, Tokyo 198-8512, Japan
Takashi Omachi	Hitachi, Ltd., 6-16-3 Shinmachi, Ome, Tokyo 198-8512, Japan

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 6, Downloads (12 Months): 12, Citation Count: 1

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Semiconductor Industry Association: "National Technology Roadmap for Semiconductors"~ (1997), Design & Test section, pp23-42.
	2	G. Friedman, "Clock Distribution Networks in VLSI Circuits and Systems", IEEE PRESS, 1995.
	3	G. Friedman, "High Performance Clock Distribution Networks", Kluwer Acadimic Publishers, 1997.
	4	Mikako Miyama , Goichi Yokomizo , Masato Iwabuchi , Masami Kinoshita, An efficient logic/circuit mixed-mode simulator for analysis of power supply voltage fluctuation, Proceedings of the 1995 conference on Asia Pacific design automation (CD-ROM), p.57-es, August 29-September 01, 1995, Makuhari, Massa, Chiba, Japan [doi>10.1145/224818.224924]
	5	Ogawa, M. Iwabuchi, et. al.: USP. 5,481,484, "Mixed Mode Simulation Method and Simulator".
	6	Abhijit Dharchoudhury , Rajendran Panda , David Blaauw , Ravi Vaidyanathan , Bogdan Tutuianu , David Bearden, Design and analysis of power distribution networks in PowerPC microprocessors, Proceedings of the 35th annual conference on Design automation, p.738-743, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277229]
	7	Liu and C. Svensson: "Power Consumption Estimation in CMOS VLSI Chips", IEEE Journal of Solid-State Circuits, (1994) pp663-670
	8	Michael K. Gowan , Larry L. Biro , Daniel B. Jackson, Power considerations in the design of the Alpha 21264 microprocessor, Proceedings of the 35th annual conference on Design automation, p.726-731, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277226]
	9	Vivek Tiwari , Deo Singh , Suresh Rajgopal , Gaurav Mehta , Rakesh Patel , Franklin Baez, Reducing power in high-performance microprocessors, Proceedings of the 35th annual conference on Design automation, p.732-737, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277227]