|
ABSTRACT
Functional partitioning assigns the functions of a system's program-like specification among system components, such as standard-software and custom-hardware processors. We introduce a new transformation, called procedure cloning, that significantly improves functional partitioning results. The transformation creates a clone of a procedure for sole use by a particular procedure caller, so the clone can be assigned to the caller's processor, which in turn improves performance through reduced communication. Heuristics are used to prevent the exponential size increase that could occur if cloning were done indiscriminately. We introduce a variety of cloning heuristics, highlight experiments demonstrating the improvements obtained using cloning, and compare the various cloning heuristics.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
|
| |
2
|
|
| |
3
|
|
| |
4
|
CHEN, Y., HSU, Y., AND KING, C. 1994. MULTIPAR: Behavioral partition for synthesizing multiprocessor architectures. IEEE Trans. Very Large Scale Integr. Syst. 2, 1 (Mar.), 21-32.
|
| |
5
|
COOPER, K., HALL, M., AND KENNEDY, K. 1993. A methodology for procedure cloning. Comput. Lang. 19, 2.
|
| |
6
|
ELES, P., PENG, Z., AND DOBOLI, A. 1992. VHDL system-level specification and partitioning in a hardware/software co-synthesis environment. In Proceedings of the International Workshop on Hardware-Software Co-Design. 49-55.
|
| |
7
|
|
| |
8
|
|
| |
9
|
|
| |
10
|
GAJSKI, D., VAHID, F., NARAYAN, S., AND GONG, J. 1998. Specsyn: An environment supporting the specify-explore-refine paradigm for hardware/software system design. IEEE Trans. Very Large Scale Integr. Syst. 6, 1, 84-100.
|
| |
11
|
|
| |
12
|
GUPTA, R. AND DEMICHELI, G. 1990. Partitioning of functional models of synchronous digital systems. In Proceedings of the International Conference on Computer-Aided Design. 216-219.
|
| |
13
|
Mary W. Hall , Jennifer M. Anderson , Saman P. Amarasinghe , Brian R. Murphy , Shih-Wei Liao , Edouard Bugnion , Monica S. Lam, Maximizing Multiprocessor Performance with the SUIF Compiler, Computer, v.29 n.12, p.84-89, December 1996
[doi> 10.1109/2.546613]
|
| |
14
|
HWANG, L. AND GAMAL, A. E. 1995. Min-cut replication in partitioned networks. IEEE Trans. CAD 14 (Jan.), 96-106.
|
 |
15
|
|
| |
16
|
|
| |
17
|
KERNIGHAN, B. AND LIN, S. 1970. An efficient heuristic procedure for partitioning graphs. Bell Syst. Tech. J. (Feb.).
|
| |
18
|
|
 |
19
|
|
 |
20
|
|
| |
21
|
LAGNESE, E. AND THOMAS, D. 1991. Architectural partitioning for system level synthesis of integrated circuits. IEEE Trans. Comput.-Aided Des. 10 (July), 847-860.
|
| |
22
|
|
| |
23
|
LIU, L., Kuo, M., Hu, T., AND CHENG, C. 1995. Performance-driven partitioning using a replication graph approach. In Proceedings of the European Conference EURO-DAC '95 with EURO-VHDL '95 on Design Automation (Brighton, UK, Sept. 18-22), G. Musgrave, Ed. IEEE Computer Society Press, Los Alamitos, CA, 206-210.
|
| |
24
|
|
 |
25
|
|
| |
26
|
|
 |
27
|
|
| |
28
|
|
| |
29
|
|
| |
30
|
|
 |
31
|
|
| |
32
|
|
| |
33
|
WOLF, W. 1994. Hardware-software co-design of embedded systems. Proc. IEEE 82, 7 (July), 967-989.
|
| |
34
|
|
| |
35
|
|
CITED BY 3
|
|
|
|
|
Yuko Hara , Hiroyuki Tomiyama , Shinya Honda , Hiroaki Takada , Katsuya Ishii, Complexity-constrainted partitioning of sequential programs for efficient behavioral synthesis, Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI, March 11-13, 2007, Stresa-Lago Maggiore, Italy
|
|
|
Yuko Hara , Hiroyuki Tomiyama , Shinya Honda , Hiroaki Takada , Katsuya Ishii, Function-Level Partitioning of Sequential Programs for Efficient Behavioral Synthesis, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, v.E90-A n.12, p.2853-2862, December 2007
|
|