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ABSTRACT
Software simulation of one computer on another tends to be slow. Traditional simulators typically execute about 100 instructions on the host machine per instruction simulated. Newer simulators reduce the expansion factor to about 10, by saving and reusing translations of individual instructions. This paper describes an experimental simulator which takes the progression one step further, translating groups of instructions as a unit. This approach, combined with flow analysis, reduces the expansion factor to about 4. The new simulator simulates System/370 on a RISC, namely the IBM RT PC.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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CITED BY 17
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Kemal Ebcioğlu , Erik R. Altman , Michael Gschwind , Sumedh Sathaye, Optimizations and oracle parallelism with dynamic translation, Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture, p.284-295, November 16-18, 1999, Haifa, Israel
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Michael Gschwind , Kemal Ebcioğlu , Erik Altman , Sumedh Sathaye, Binary translation and architecture convergence issues for IBM system/390, Proceedings of the 14th international conference on Supercomputing, p.336-347, May 08-11, 2000, Santa Fe, New Mexico, United States
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Swaroop Sridhar , Jonathan S. Shapiro , Eric Northup , Prashanth P. Bungale, HDTrans: an open source, low-level dynamic instrumentation system, Proceedings of the second international conference on Virtual execution environments, June 14-16, 2006, Ottawa, Ontario, Canada
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