Circuit partitioning for dynamically reconfigurable FPGAs

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Circuit partitioning for dynamically reconfigurable FPGAs

Full text

Pdf (990 KB)

Source

International Symposium on Field Programmable Gate Arrays archive
Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays table of contents

Monterey, California, United States

Pages: 187 - 194

Year of Publication: 1999

ISBN:1-58113-088-0

Authors

Huiqun Liu	Department of Computer Sciences, University of Texas at Austin, Austin, TX
D. F. Wong	Department of Computer Sciences, University of Texas at Austin, Austin, TX

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 28, Citation Count: 4

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/296399.296456 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Steve Trimberger, Scheduling designs into a time-multiplexed FPGA, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.153-160, February 22-25, 1998, Monterey, California, United States [doi>10.1145/275107.275135]
	2	Douglas Chang , Malgorzata Marek-Sadowska, Partitioning sequential circuits on dynamically reconfiguable FPGAs, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.161-167, February 22-25, 1998, Monterey, California, United States [doi>10.1145/275107.275136]
	3	Douglas Chang , Malgorzata Marek-Sadowska, Buffer minimization and time-multiplexed I/O on dynamically reconfigurable FPGAs, Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, p.142-148, February 09-11, 1997, Monterey, California, United States [doi>10.1145/258305.258331]
	4	Sasan Iman, Massoud Pedram, Charles Fabian and Jason Cong, "Finding Uni-Directional Cuts Based on Physical Partitioning and Logic Restructuring", dth International workshop on physical design, 1993.
	5	J.R. Ford and D.R. Fulkerson, "Flows in Networks", Princeton University Press, 1962.
	6	Narasimha B. Bhaqt , Kamal Chaudary , Ernest S. Kuh, Performance-Oriented Fully Routable Dynamic Architecture for a Field, University of California at Berkeley, Berkeley, CA, 1993
	7	jeremy Brown, Derrick Chen, et al. "DELTA: Prototype for a first- generation dynamically programmable gate array", Transit Note 112, MIT, 1995.
	8	Andre DeHon, "DPGA-coupled microprocessors: Commodity ICs for the early 21st century", In IEEE Workshop on FPGAs for Custom Computing Machines, 1994.
	9	D. jones and D.M. Lewis, "A time-multiplexed FPGA architecture for logic emulation", In IEEE Custom Integrated Circuits Conference, 1995.
	10	Ren-Song Tsay , Ernest S. Kuh , Chi-Ping Hsu, Proud: a fast sea-of-gates placement algorithm, Proceedings of the 25th ACM/IEEE conference on Design automation, p.318-323, June 12-15, 1988, Atlantic City, New Jersey, United States
	11	Michael R. Garey , David S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness, W. H. Freeman & Co., New York, NY, 1979
	12	C. M. Fiduccia , R. M. Mattheyses, A linear-time heuristic for improving network partitions, Proceedings of the 19th conference on Design automation, p.175-181, January 1982
	13	B. W. Kernighan and S. Lin, "An efficient heuristic procedure for partitioning graphs", IEEE Transaction on Computers, pp1064-1068, Nov. 1978.
	14	Honghua Yang , D. F. Wong, Efficient network flow based min-cut balanced partitioning, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.50-55, November 06-10, 1994, San Jose, California, United States
	15	Xilinx, The Programmable Logic Data Book, 1996.
	16	Huiqun Liu , D. F. Wong, Network flow based circuit partitioning for time-multiplexed FPGAs, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.497-504, November 08-12, 1998, San Jose, California, United States [doi>10.1145/288548.289077]

CITED BY 4

	Huiqun Liu , D. F. Wong, A graph theoretic optimal algorithm for schedule compression in time-multiplexed FPGA partitioning, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.400-405, November 07-11, 1999, San Jose, California, United States
	Kiarash Bazargan , Ryan Kastner , Majid Sarrafzadeh, Fast Template Placement for Reconfigurable Computing Systems, IEEE Design & Test, v.17 n.1, p.68-83, January 2000
	Katherine Compton , Scott Hauck, Reconfigurable computing: a survey of systems and software, ACM Computing Surveys (CSUR), v.34 n.2, p.171-210, June 2002
	Rajarshi Mukherjee , Song Liu , Seda Ogrenci Memik , Somsubhra Mondal, A high-level clustering algorithm targeting dual V_dd FPGAs, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.13 n.4, p.1-20, September 2008