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Trading quality for compile time: ultra-fast placement for FPGAs
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Source International Symposium on Field Programmable Gate Arrays archive
Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays table of contents
Monterey, California, United States
Pages: 157 - 166  
Year of Publication: 1999
ISBN:1-58113-088-0
Authors
Yaska Sankar  Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada M5S 3G4
Jonathan Rose  Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, Canada M5S 3G4
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 1,   Downloads (12 Months): 16,   Citation Count: 14
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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V. Betz, "Architecture and CAD for Speed and Area Optimization of FPGAs," Ph.D. Thesis, University of Toronto, 1998.
 
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J. Cong and Y. Ding, "Flowmap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs," IEEE Trans. on CAD, Jan. 1994, pp. 1-12.
 
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A. E. Dunlop and B. W. Kemighan, "A Procedure for Placement of Standard-Cell VLSI Circuits" IEEE Trans. on CAD, vol. 4, no. 1, Jan. 1985, pp. 92-98.
Gehr98
 
Hame98
I. Hamer, "Implementation of DES on Transmogrifier- 2a," Personal Communication, 1998.
 
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M. Hanan and J. M. Kurtzberg, "Placement Techniques," in Design Automation of Digital Systems, Volume 1: Theory and Techniques, M. A. Breuer, Ed., Prentice-Hall, 1972, pp. 213-281.
Hutt97
 
Kirk83
S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi, "Optimization by Simulated Annealing" Science, vol. 220, no. 4598, May 13, 1983, pp. 671-680.
 
Klei91
J. M. Kleinhans, G. Sigl, F. M. Johannes, and K. J. Antreich, "GORDIAN: VLSI Placement by Quadratic Programming and Slicing Optimization," IEEE Trans. on CAD, vol. 10, no. 3, Mar. 1991, pp. 356-365.
Lewi97
 
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P. Leventis, "Using edif2blif Version 1.0," University of Toronto, 1998. (Available for download from http:# www. eecg. toronto, edu./~leventi/edif2blif/edif2blif, htmI).
 
Roy93
 
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J. Rose, W. Klebsch, and J. Wolff "Temperature Measurement and Equilibrium Dynamics of Simulated Annealing Placements," IEEE Trans. on CAD, vol. 9, no. 3, Mar. 1990, pp. 253-259.
 
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Y. Sankar, "Ultra-Fast Automatic Placement for FPGAs," M.A.Sc. Thesis, University of Toronto, in preparation, 1999.
 
Sech85
C. Sechen and A. Sangiovanni-Vincentelli, "The Timber- Wolf Placement and Routing Package," IEEE Journal of Solid-State Circuits, vol. 20, no. 2, Apr. 1985, pp. 510-522.
 
Sech88
C. Sechen, VLSI Placement and Global Routing Using Simulated Annealing, Kluwer Academic Publishers, 1988.
 
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E. M. Sentovich et al., "SIS: A System for Sequential Circuit Analysis," Tech. Report No. UCB/ERL M92/41, University of California, Berkeley, 1992.
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W. Sun and C. Sechen, "Efficient and Effective Placement for Very Large Circuits;' IEEE Trans. on CAD, vol. 14, no. 3, Mar. 1995, pp. 349-359.
Swar98a
 
Swar98b
J. S. Swartz, "A High-Speed Timing-Aware Router for FleAs," M.A.Sc. Thesis, University of Toronto, 1998.
 
Tess98
 
Yang91
S. Yang, "Logic Synthesis and Optimization Benchmarks, Version 3.0," Tech. Report, Microelectronics Centre of North Carolina, 199 I.
 
Ye99
A. Ye, "Procedural Texture Mapping on FPGAs," M.A.Sc. Thesis, University of Toronto, in preparation, 1999.

CITED BY  14

Collaborative Colleagues:
Yaska Sankar: colleagues
Jonathan Rose: colleagues