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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Babb97
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J. Babb , M. Frank , V. Lee , E. Waingold , R. Barua , M. Taylor , J. Kim , S. Devabhaktuni , A. Agarwal, The RAW benchmark suite: computation structures for general purpose computing, Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines, p.134, April 16-18, 1997
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Betz97
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Betz98
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V. Betz, "Architecture and CAD for Speed and Area Optimization of FPGAs," Ph.D. Thesis, University of Toronto, 1998.
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Brow92
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Call98
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Timothy J. Callahan , Philip Chong , André DeHon , John Wawrzynek, Fast module mapping and placement for datapaths in FPGAs, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.123-132, February 22-25, 1998, Monterey, California, United States
[doi> 10.1145/275107.275132]
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Cong94
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J. Cong and Y. Ding, "Flowmap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs," IEEE Trans. on CAD, Jan. 1994, pp. 1-12.
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Dunl85
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A. E. Dunlop and B. W. Kemighan, "A Procedure for Placement of Standard-Cell VLSI Circuits" IEEE Trans. on CAD, vol. 4, no. 1, Jan. 1985, pp. 92-98.
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Gehr98
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Hame98
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I. Hamer, "Implementation of DES on Transmogrifier- 2a," Personal Communication, 1998.
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Hana72
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M. Hanan and J. M. Kurtzberg, "Placement Techniques," in Design Automation of Digital Systems, Volume 1: Theory and Techniques, M. A. Breuer, Ed., Prentice-Hall, 1972, pp. 213-281.
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Hutt97
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Michael Hutton , Jonathan Rose , Derek Corneil, Generation of synthetic sequential benchmark circuits, Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, p.149-155, February 09-11, 1997, Monterey, California, United States
[doi> 10.1145/258305.258333]
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Kirk83
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S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi, "Optimization by Simulated Annealing" Science, vol. 220, no. 4598, May 13, 1983, pp. 671-680.
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Klei91
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J. M. Kleinhans, G. Sigl, F. M. Johannes, and K. J. Antreich, "GORDIAN: VLSI Placement by Quadratic Programming and Slicing Optimization," IEEE Trans. on CAD, vol. 10, no. 3, Mar. 1991, pp. 356-365.
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Lewi97
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David M. Lewis , David R. Galloway , Marcus van Ierssel , Jonathan Rose , Paul Chow, The Transmogrifier-2: a 1 million gate rapid prototyping system, Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, p.53-61, February 09-11, 1997, Monterey, California, United States
[doi> 10.1145/258305.258312]
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Leve98
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P. Leventis, "Using edif2blif Version 1.0," University of Toronto, 1998. (Available for download from http:# www. eecg. toronto, edu./~leventi/edif2blif/edif2blif, htmI).
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Roy93
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Rose90
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J. Rose, W. Klebsch, and J. Wolff "Temperature Measurement and Equilibrium Dynamics of Simulated Annealing Placements," IEEE Trans. on CAD, vol. 9, no. 3, Mar. 1990, pp. 253-259.
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Sank99
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Y. Sankar, "Ultra-Fast Automatic Placement for FPGAs," M.A.Sc. Thesis, University of Toronto, in preparation, 1999.
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Sech85
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C. Sechen and A. Sangiovanni-Vincentelli, "The Timber- Wolf Placement and Routing Package," IEEE Journal of Solid-State Circuits, vol. 20, no. 2, Apr. 1985, pp. 510-522.
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Sech88
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C. Sechen, VLSI Placement and Global Routing Using Simulated Annealing, Kluwer Academic Publishers, 1988.
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Sent92
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E. M. Sentovich et al., "SIS: A System for Sequential Circuit Analysis," Tech. Report No. UCB/ERL M92/41, University of California, Berkeley, 1992.
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Shah91
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Sun95
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W. Sun and C. Sechen, "Efficient and Effective Placement for Very Large Circuits;' IEEE Trans. on CAD, vol. 14, no. 3, Mar. 1995, pp. 349-359.
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Swar98a
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Jordan S. Swartz , Vaughn Betz , Jonathan Rose, A fast routability-driven router for FPGAs, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.140-149, February 22-25, 1998, Monterey, California, United States
[doi> 10.1145/275107.275134]
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Swar98b
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J. S. Swartz, "A High-Speed Timing-Aware Router for FleAs," M.A.Sc. Thesis, University of Toronto, 1998.
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Tess98
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Yang91
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S. Yang, "Logic Synthesis and Optimization Benchmarks, Version 3.0," Tech. Report, Microelectronics Centre of North Carolina, 199 I.
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Ye99
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A. Ye, "Procedural Texture Mapping on FPGAs," M.A.Sc. Thesis, University of Toronto, in preparation, 1999.
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CITED BY 14
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Andy Yan , Rebecca Cheng , Steven J. E. Wilton, On the sensitivity of FPGA architectural conclusions to experimental assumptions, tools, and techniques, Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays, February 24-26, 2002, Monterey, California, USA
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