HSRA

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HSRA: high-speed, hierarchical synchronous reconfigurable array

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International Symposium on Field Programmable Gate Arrays archive
Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays table of contents

Monterey, California, United States

Pages: 125 - 134

Year of Publication: 1999

ISBN:1-58113-088-0

Authors

William Tsu	Berkeley Reconfigurable, Architectures, Software, and Systems, Computer Science Division, University of California at Berkeley, Berkeley, CA
Kip Macy	Berkeley Reconfigurable, Architectures, Software, and Systems, Computer Science Division, University of California at Berkeley, Berkeley, CA
Atul Joshi	Berkeley Reconfigurable, Architectures, Software, and Systems, Computer Science Division, University of California at Berkeley, Berkeley, CA
Randy Huang	Berkeley Reconfigurable, Architectures, Software, and Systems, Computer Science Division, University of California at Berkeley, Berkeley, CA
Norman Walker	Berkeley Reconfigurable, Architectures, Software, and Systems, Computer Science Division, University of California at Berkeley, Berkeley, CA
Tony Tung	Berkeley Reconfigurable, Architectures, Software, and Systems, Computer Science Division, University of California at Berkeley, Berkeley, CA
Omid Rowhani	Berkeley Reconfigurable, Architectures, Software, and Systems, Computer Science Division, University of California at Berkeley, Berkeley, CA
Varghese George	Berkeley Reconfigurable, Architectures, Software, and Systems, Computer Science Division, University of California at Berkeley, Berkeley, CA
John Wawrzynek	Berkeley Reconfigurable, Architectures, Software, and Systems, Computer Science Division, University of California at Berkeley, Berkeley, CA
André DeHon	Berkeley Reconfigurable, Architectures, Software, and Systems, Computer Science Division, University of California at Berkeley, Berkeley, CA

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 34, Citation Count: 30

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 30

	Akshay Sharma , Carl Ebeling , Scott Hauck, PipeRoute: a pipelining-aware router for FPGAs, Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays, February 23-25, 2003, Monterey, California, USA
	Amit Singh , Arindam Mukherjee , Malgorzata Marek-Sadowska, Interconnect pipelining in a throughput-intensive FPGA architecture, Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays, p.153-160, February 2001, Monterey, California, United States
	Amit Singh , Luca Macchiarulo , Arindam Mukherjee , Malgorzata Marek-Sadowska, A novel high throughput reconfigurable FPGA architecture, Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, p.22-29, February 10-11, 2000, Monterey, California, United States
	Deshanand P. Singh , Stephen D. Brown, The case for registered routing switches in field programmable gate arrays, Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays, p.161-169, February 2001, Monterey, California, United States
	Randy Huang , John Wawrzynek , André DeHon, Stochastic, spatial routing for hypergraphs, trees, and meshes, Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays, February 23-25, 2003, Monterey, California, USA
	Nicholas Weaver , Yury Markovskiy , Yatish Patel , John Wawrzynek, Post-placement C-slow retiming for the xilinx virtex FPGA, Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays, February 23-25, 2003, Monterey, California, USA
	Amit Singh , Arindam Mukherjee , Luca Macchiarulo , Malgorzata Marek-Sadowska, PITIA: an FPGA for throughput-intensive applications, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.3, p.354-363, June 2003
	Xin Jia , Ranga Vemuri, Using GALS architecture to reduce the impact of long wire delay on FPGA performance, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Akshay Sharma , Katherine Compton , Carl Ebeling , Scott Hauck, Exploration of pipelined FPGA interconnect structures, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, February 22-24, 2004, Monterey, California, USA
	André DeHon, Unifying mesh- and tree-based programmable interconnect, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.10, p.1051-1065, October 2004
	Nicholas Weaver , John Hauser , John Wawrzynek, The SFRA: a corner-turn FPGA architecture, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, February 22-24, 2004, Monterey, California, USA
	André DeHon , Raphael Rubin, Design of FPGA interconnect for multilevel metallization, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.10, p.1038-1050, October 2004
	Raphael Rubin , André DeHon, Design of FPGA interconnect for multilevel metalization, Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays, February 23-25, 2003, Monterey, California, USA
	André DeHon, The Density Advantage of Configurable Computing, Computer, v.33 n.4, p.41-49, April 2000
	John Teifel , Rajit Manohar, Highly pipelined asynchronous FPGAs, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, February 22-24, 2004, Monterey, California, USA
	John Teifel , Rajit Manohar, An Asynchronous Dataflow FPGA Architecture, IEEE Transactions on Computers, v.53 n.11, p.1376-1392, November 2004
	Ken Eguro , Scott Hauck, Armada: timing-driven pipeline-aware routing for FPGAs, Proceedings of the internation symposium on Field programmable gate arrays, February 22-24, 2006, Monterey, California, USA
	Ken Eguro , Scott Hauck , Akshay Sharma, Architecture-adaptive range limit windowing for simulated annealing FPGA placement, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	André Dehon, Nanowire-based programmable architectures, ACM Journal on Emerging Technologies in Computing Systems (JETC), v.1 n.2, p.109-162, July 2005
	Katherine Compton , Scott Hauck, Reconfigurable computing: a survey of systems and software, ACM Computing Surveys (CSUR), v.34 n.2, p.171-210, June 2002
	John M. Emmert , Dinesh K. Bhatia, A Fault Tolerant Technique for FPGAs, Journal of Electronic Testing: Theory and Applications, v.16 n.6, p.591-606, Dec. 2000
	Mahim Mishra , Timothy J. Callahan , Tiberiu Chelcea , Girish Venkataramani , Seth C. Goldstein , Mihai Budiu, Tartan: evaluating spatial computation for whole program execution, ACM SIGOPS Operating Systems Review, v.40 n.5, December 2006
	Richard B. Kujoth , Chi-Wei Wang , Jeffrey J. Cook , Derek B. Gottlieb , Nicholas P. Carter, A wire delay-tolerant reconfigurable unit for a clustered programmable-reconfigurable processor, Microprocessors & Microsystems, v.31 n.2, p.146-159, March, 2007
	Hayder Mrabet , Zied Marrakchi , Pierre Souillot , Habib Mehrez, Performances improvement of FPGA using novel multilevel hierarchical interconnection structure, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
	Xin Jia , Ranga Vemuri, Studying a GALS FPGA architecture using a parameterized automatic design flow, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
	R. Huang , R. Vemuri, Analysis and evaluation of a hybrid interconnect structure for FPGAs, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.595-601, November 07-11, 2004
	A. DeHon , K. K. Likharev, Hybrid CMOS/nanoelectronic digital circuits: devices, architectures, and design automation, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.375-382, November 06-10, 2005, San Jose, CA
	André DeHon, Compact, multilayer layout for butterfly fat-tree, Proceedings of the twelfth annual ACM symposium on Parallel algorithms and architectures, p.206-215, July 09-13, 2000, Bar Harbor, Maine, United States
	Ian Kuon , Russell Tessier , Jonathan Rose, FPGA Architecture: Survey and Challenges, Foundations and Trends® in Electronic Design Automation, v.2 n.2, p.135-253, February 2008
	Stephen Friedman , Allan Carroll , Brian Van Essen , Benjamin Ylvisaker , Carl Ebeling , Scott Hauck, SPR: an architecture-adaptive CGRA mapping tool, Proceeding of the ACM/SIGDA international symposium on Field programmable gate arrays, February 22-24, 2009, Monterey, California, USA