Configuration cloning

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Configuration cloning: exploiting regularity in dynamic DSP architectures

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International Symposium on Field Programmable Gate Arrays archive
Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays table of contents

Monterey, California, United States

Pages: 81 - 89

Year of Publication: 1999

ISBN:1-58113-088-0

Authors

S. R. Park	Dept. of ECE, University of Massachusetts, Amherst, MA
W. Burleson	Dept. of ECE, University of Massachusetts, Amherst, MA

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 14, Citation Count: 5

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	2	Xilinx, XC6200 Field Programmable Gate Arrays Data Sheet, Ver. 1.8, 1996.
	3	Xi}finx, XC4000E and XC4000X series Field Programmable Gate Arrays Data Sheet, Ver. 1.4, Nov. 1997.
	4	Lucent Technologies, ORCA OR2CxxA and OR2TxxA Series Field-Programmable Gate Array Data Sheet, Jan. 1998.
	5	ATMEL, AT6000/LV Series Data Sheet.
	6	H. Schmit, Incremental reconfiguration for pipelined applications, Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines, p.47, April 16-18, 1997
	7	André DeHon, DPGA utilization and application, Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays, p.115-121, February 11-13, 1996, Monterey, California, United States [doi>10.1145/228370.228387]
	8	G.R.Goslin, "A Guide to Using Field Programmable Gate Arrays(FPGAs) for Application-Specific Digital Signal Processing Performance", Proceedings of High- Speed computing, Digital Signal Processing and Filtering Using reconfigurable Logic, 1996, SPIE Vol.2914, pp.321-331.
	9	P. Pirsch, N. Demassieux, and W. Gehrke, "VLSI Architectures for Video Compression -A Survey," Proc. of IEEE, vol.83, pp.220-246, Feb, 1995.
	10	S.R. Park and W. Burleson, "Reconfiguration for Power Saving in Real-Time Motion Estimation", ICASSP, 1997.
	11	J. Villasenor, B. Schoner, et al, "Configurable computing solutions for automatic target recognition , Proceeding of IEEE workshop on FPGAs for Custom computing machines, pp.70-79,1996.
	12	M. Petronino, R. Bambha, J. Carswell, and W. Burleson, "An FPGA-based Data Acquisition systems for 95GHz W-band Radar", ICASSP, 1997.
	13	A. Brahmbhatt, and W. Burleson, "FPGA-based Coprocessors for Wireless Data Communications", Massachusetts Telecommunications Conference, 1997.
	14	M.J. Wirth}fin, and B.L. Hutchings, "DISC: The dynamic instruction set computer", Field Programmable GateArrays (FPGAs) for Fast Board Development and Reconfigurable Computing, Proc. SPIE 2607, pp. 92- 103, 1995.
	15	Y. Baek, H.-S Oh, and H.-K. Lee, "An efficient blockmatching criterion for motion estimation and its VLSI implementation", IEEE Trans. Consum. Elec. Vo1.42, pp.885-892, Nov. 1996.
	16	B. Schoner , C. Jones , J. Villasenor, Issues in wireless video coding using run-time-reconfigurable FPGAs, Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines, p.85, April 19-21, 1995
	17	National Semiconductor, "Configurable Logic Array(CLAy) Data Sheet, 1993.
	18	M.J. Wirth}fin and B.L. Hutchings, "Improving Functional Density Through Run-Time Constant Propagation", FPGA'97, 1997.
	19	J. Villasenor and B.L. Hutchings, "The Flexibility of Configurable Computing", IEEE Signal Processing Magazine, pp.67-84, Sep. 1998.
	20	Jason Leonard , William H. Mangione-Smith, A case study of partially evaluated hardware circuits: Key-specific DES, Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications, p.151-160, September 01-03, 1997
	21	personal communication with C. Paar, http://ee.wpi.edu/People/faculty/cxp.html
	22	http://www.cs.berkeley, edu/projects/brass /
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	25	M. Goel, N. Shanbhag, "Low-Power Equalizers for 51.84 MB/s Very High-Speed Digital Subscriber Loop (VDSL) Modems, IEEE Workshop on Signal Processing Systems, 1998.

CITED BY 5

	Ranga Vemuri , Sriram Govindarajan , Iyad Ouaiss , Meenakshi Kaul , Vinoo Srinivasan , Shankar Radhakrishnan , Sujatha Sundaraman , Satish Ganesan , Awartika Pandey , Preetham Lakshmikanthan, Automated design synthesis and partitioning for adaptive reconfigurable hardware, Hardware implementation of intelligent systems, Physica-Verlag GmbH, Heidelberg, Germany, 2001
	Gianluca Tempesti , Daniel Mange , Pierre-André Mudry , Joël Rossier , André Stauffer, Self-replication for reliability: bio-inspired hardware and the embryonics project, Proceedings of the 3rd conference on Computing frontiers, May 03-05, 2006, Ischia, Italy
	Gianluca Tempesti , Daniel Mange , Pierre-Andre Mudry , Joël Rossier , Andre Stauffer, Self-replicating hardware for reliability: The embryonics project, ACM Journal on Emerging Technologies in Computing Systems (JETC), v.3 n.2, p.9-es, July 2007
	Lei He , T. Mitra , Weng-Fai Wong, Configuration bitstream compression for dynamically reconfigurable FPGAs, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.766-773, November 07-11, 2004
	Russell Tessier , Wayne Burleson, Reconfigurable Computing for Digital Signal Processing: A Survey, Journal of VLSI Signal Processing Systems, v.28 n.1-2, p.7-27, May-June 2001