Balancing interconnect and computation in a reconfigurable computing array (or, why you don't really want 100% LUT utilization)

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Balancing interconnect and computation in a reconfigurable computing array (or, why you don't really want 100% LUT utilization)

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International Symposium on Field Programmable Gate Arrays archive
Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays table of contents

Monterey, California, United States

Pages: 69 - 78

Year of Publication: 1999

ISBN:1-58113-088-0

Author

André DeHon

Berkeley Reconfigurable, Architectures, Software, and Systems, Computer Science Division, University of California at Berkeley, Berkeley, CA

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 47, Citation Count: 29

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references cited by index terms collaborative colleagues

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REFERENCES

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	S. Kumar , L. Pires , S. Ponnuswamy , C. Nanavati , J. Golusky , M. Vojta , S. Wadi , D. Pandalai , H. Spaanenberg, A benchmark suite for evaluating configurable computing systems—status, reflections, and future directions, Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, p.126-134, February 10-11, 2000, Monterey, California, United States
	André DeHon, Rent's rule based switching requirements, Proceedings of the 2001 international workshop on System-level interconnect prediction, p.197-204, March 31-April 01, 2001, Sonoma, California, United States
	Michael Hutton, Interconnect prediction for programmable logic devices, Proceedings of the 2001 international workshop on System-level interconnect prediction, p.125-131, March 31-April 01, 2001, Sonoma, California, United States
	G. Parthasarathy , M. Marek-Sadowska , Arindam Mukherjee , Amit Singh, Interconnect complexity-aware FPGA placement using Rent's rule, Proceedings of the 2001 international workshop on System-level interconnect prediction, p.115-121, March 31-April 01, 2001, Sonoma, California, United States
	Amit Singh , Ganapathy Parthasarathy , Malgorzata Marek-Sadowska, Efficient circuit clustering for area and power reduction in FPGAs, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.7 n.4, p.643-663, October 2002
	Amit Singh , Ganapathy Parthasarathy , Malgorzata Marek-Sadowska, Interconnect resource-aware placement for hierarchical FPGAs, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Amit Singh , Malgorzata Marek-Sadowska, Efficient circuit clustering for area and power reduction in FPGAs, Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays, February 24-26, 2002, Monterey, California, USA
	Randy Huang , John Wawrzynek , André DeHon, Stochastic, spatial routing for hypergraphs, trees, and meshes, Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays, February 23-25, 2003, Monterey, California, USA
	Guy Lemieux , Paul Leventis , David Lewis, Generating highly-routable sparse crossbars for PLDs, Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, p.155-164, February 10-11, 2000, Monterey, California, United States
	André DeHon, Unifying mesh- and tree-based programmable interconnect, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.10, p.1051-1065, October 2004
	André DeHon, Design of programmable interconnect for sublithographic programmable logic arrays, Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays, February 20-22, 2005, Monterey, California, USA
	Joachim Pistorius , Mike Hutton, Placement rent exponent calculation methods, temporal behaviour and FPGA architecture evaluation, Proceedings of the 2003 international workshop on System-level interconnect prediction, April 05-06, 2003, Monterey, CA, USA
	Marvin Tom , Guy Lemieux, Logic block clustering of large designs for channel-width constrained FPGAs, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Ken Eguro , Scott Hauck , Akshay Sharma, Architecture-adaptive range limit windowing for simulated annealing FPGA placement, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Dmitri B. Strukov , Konstantin K. Likharev, A reconfigurable architecture for hybrid CMOS/Nanodevice circuits, Proceedings of the internation symposium on Field programmable gate arrays, February 22-24, 2006, Monterey, California, USA
	Jing Huang , Mehdi Baradaran Tahoori , Fabrizio Lombardi, Fault tolerance of switch blocks and switch block arrays in FPGA, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.13 n.7, p.794-807, July 2005
	Katherine Compton , Scott Hauck, Reconfigurable computing: a survey of systems and software, ACM Computing Surveys (CSUR), v.34 n.2, p.171-210, June 2002
	M. Y. Lanzerotti , G. Fiorenza , R. A. Rand, Microminiature packaging and integrated circuitry: the work of E. F. Rent, with an application to on-chip interconnection requirements, IBM Journal of Research and Development, v.49 n.4/5, p.777-803, July 2005
	Peter Zipf, Applying dynamic reconfiguration for fault tolerance in fine-grained logic arrays, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.16 n.2, p.134-143, February 2008
	Mehdi Tahoori, Application-dependent testing of FPGAs, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.14 n.9, p.1024-1033, September 2006
	Yue Zhuo , Hao Li , Qiang Zhou , Yici Cai , Xianlong Hong, New timing and routability driven placement algorithms for FPGA synthesis, Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI, March 11-13, 2007, Stresa-Lago Maggiore, Italy
	Hayder Mrabet , Zied Marrakchi , Pierre Souillot , Habib Mehrez, Performances improvement of FPGA using novel multilevel hierarchical interconnection structure, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
	Marvin Tom , David Leong , Guy Lemieux, Un/DoPack: re-clustering of large system-on-chip designs with interconnect variation for low-cost FPGAs, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
	R. Huang , R. Vemuri, Analysis and evaluation of a hybrid interconnect structure for FPGAs, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.595-601, November 07-11, 2004
	Hongbing Fan , Yu-Liang Wu , Ray Chak-Chung Cheung , Jiping Liu, Decomposition Design Theory and Methodology for Arbitrary-Shaped Switch Boxes, IEEE Transactions on Computers, v.55 n.4, p.373-384, April 2006
	Wing On Fung , Tughrul Arslan, A power-aware algorithm for the design of reconfigurable hardware during high level placement, International Journal of Knowledge-based and Intelligent Engineering Systems, v.12 n.3, p.237-244, August 2008
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