FPGA routing architecture

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FPGA routing architecture: segmentation and buffering to optimize speed and density

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International Symposium on Field Programmable Gate Arrays archive
Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays table of contents

Monterey, California, United States

Pages: 59 - 68

Year of Publication: 1999

ISBN:1-58113-088-0

Authors

Vaughn Betz	Department of Electrical and Computer Engineering, University of Toronto, Toronto, Ontario, Canada M5S 3G4
Jonathan Rose	Department of Electrical and Computer Engineering, University of Toronto, Toronto, Ontario, Canada M5S 3G4

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 7, Downloads (12 Months): 59, Citation Count: 25

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	2	Jonathan Rose , Dwight Hill, Architectural and physical design challenges for one-million gate FPGAs and beyond, Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, p.129-132, February 09-11, 1997, Monterey, California, United States [doi>10.1145/258305.258324]
	3	Xilinx Inc., The Programmable Logic Data Book, 1994.
	4	Lucent Technologies, FPGA Data Book, 1998.
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	7	Vaughn Betz , Jonathan Rose , Alexander Marquardt, Architecture and CAD for Deep-Submicron FPGAs, Kluwer Academic Publishers, Norwell, MA, 1999
	8	J. Rose and S. Brown, "Flexibility of Interconnection Structures for Field-Programmable Gate Arrays," JSSC, March 1991, pp. 277 - 282.
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	33	Xilinx Inc., "XC4000E and XC4000X Series Field-Programmable Gate Arrays," Data Sheet, 1997.
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	35	J. Swartz, "A High-Speed Timing-Aware Router for FPGAs," M.A.Sc. Thesis, University of Toronto, 1998.

CITED BY 25

	Mike Sheng , Jonathan Rose, Mixing buffers and pass transistors in FPGA routing architectures, Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays, p.75-84, February 2001, Monterey, California, United States
	Peter Hallschmid , Steven J. E. Wilton, Detailed routing architectures for embedded programmable logic IP cores, Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays, p.69-74, February 2001, Monterey, California, United States
	Amit Singh , Malgorzata Marek-Sadowska, FPGA interconnect planning, Proceedings of the 2002 international workshop on System-level interconnect prediction, April 06-07, 2002, San Diego, California, USA
	Chetan Patel , Anthony Cozzie , Herman Schmit , Larry Pileggi, An architectural exploration of via patterned gate arrays, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA
	David Lewis , Elias Ahmed , Gregg Baeckler , Vaughn Betz , Mark Bourgeault , David Cashman , David Galloway , Mike Hutton , Chris Lane , Andy Lee , Paul Leventis , Sandy Marquardt , Cameron McClintock , Ketan Padalia , Bruce Pedersen , Giles Powell , Boris Ratchev , Srinivas Reddy , Jay Schleicher , Kevin Stevens , Richard Yuan , Richard Cliff , Jonathan Rose, The Stratix II logic and routing architecture, Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays, February 20-22, 2005, Monterey, California, USA
	Pongstorn Maidee , Cristinel Ababei , Kia Bazargan, Fast timing-driven partitioning-based placement for island style FPGAs, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Deming Chen , Jason Cong , Yiping Fan, Low-power high-level synthesis for FPGA architectures, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	Luca Macchiarulo , Consolato F. Caccamo , Davide Pandini, A comparison between mask- and field-programmable routing structures on industrial FPGA architectures, Proceedings of the 14th ACM Great Lakes symposium on VLSI, April 26-28, 2004, Boston, MA, USA
	Akshay Sharma , Katherine Compton , Carl Ebeling , Scott Hauck, Exploration of pipelined FPGA interconnect structures, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, February 22-24, 2004, Monterey, California, USA
	Fei Li , Deming Chen , Lei He , Jason Cong, Architecture evaluation for power-efficient FPGAs, Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays, February 23-25, 2003, Monterey, California, USA
	Andy Ye , Jonathan Rose, Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits, Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays, February 20-22, 2005, Monterey, California, USA
	André DeHon , Raphael Rubin, Design of FPGA interconnect for multilevel metallization, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.10, p.1038-1050, October 2004
	Raphael Rubin , André DeHon, Design of FPGA interconnect for multilevel metalization, Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays, February 23-25, 2003, Monterey, California, USA
	David Lewis , Vaughn Betz , David Jefferson , Andy Lee , Chris Lane , Paul Leventis , Sandy Marquardt , Cameron McClintock , Bruce Pedersen , Giles Powell , Srinivas Reddy , Chris Wysocki , Richard Cliff , Jonathan Rose, The stratixπ routing and logic architecture, Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays, February 23-25, 2003, Monterey, California, USA
	André DeHon, Design of programmable interconnect for sublithographic programmable logic arrays, Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays, February 20-22, 2005, Monterey, California, USA
	André Dehon, Nanowire-based programmable architectures, ACM Journal on Emerging Technologies in Computing Systems (JETC), v.1 n.2, p.109-162, July 2005
	Jai-Ming Lin , Song-Ra Pan , Yao-Wen Chang, Graph matching-based algorithms for array-based FPGA segmentation design and routing, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Wei Zhang , Niraj K. Jha , Li Shang, NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Katherine Compton , Scott Hauck, Reconfigurable computing: a survey of systems and software, ACM Computing Surveys (CSUR), v.34 n.2, p.171-210, June 2002
	Peter Hallschmid , Steve J. E. Wilton, Routing architecture optimizations for high-density embedded programmable IP cores, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.13 n.11, p.1320-1324, November 2005
	Siva Nageswara Rao Borra , Annamalai Muthukaruppan , S. Suresh , V. Kamakoti, A novel approach to the placement and routing problems for field programmable gate arrays, Applied Soft Computing, v.7 n.1, p.455-470, January, 2007
	Ho-Yan Wong , Lerong Cheng , Yan Lin , Lei He, FPGA device and architecture evaluation considering process variations, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.19-24, November 06-10, 2005, San Jose, CA
	Ian Kuon , Russell Tessier , Jonathan Rose, FPGA Architecture: Survey and Challenges, Foundations and Trends® in Electronic Design Automation, v.2 n.2, p.135-253, February 2008
	Mingjie Lin , Abbas El Gamal, TORCH: a design tool for routing channel segmentation in FPGAs, Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays, February 24-26, 2008, Monterey, California, USA
	Mingjie Lin, The amorphous FPGA architecture, Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays, February 24-26, 2008, Monterey, California, USA