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Cut ranking and pruning: enabling a general and efficient FPGA mapping solution

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International Symposium on Field Programmable Gate Arrays archive
Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays table of contents

Monterey, California, United States

Pages: 29 - 35

Year of Publication: 1999

ISBN:1-58113-088-0

Authors

Jason Cong	Department of Computer Science, University of California, Los Angeles, CA
Chang Wu	Department of Computer Science, University of California, Los Angeles, CA
Yuzheng Ding	Bell Laboratories, Lucent Technologies, Murray Hill, NJ

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 61, Citation Count: 41

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	J. Cong and Y. Ding. FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs. IEEE Trans. on Computer-Aided Design of Integrated Circuits And Systems, 13(1):1-12, 1994.
	2	J. Cong and Y. Ding. On Area/Delay Trade-off in LUT- based FPGA Technology Mapping. IEEE Trans. on VLSi Systems, 2(2):137-148, June 1994.
	3	Jason Cong , Yuzheng Ding, Combinational logic synthesis for LUT based field programmable gate arrays, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.2, p.145-204, April 1996 [doi>10.1145/233539.233540]
	4	K. Eckl, C. Legl, A. Lu, and B. Rohfleisch. TOS-2.2 Technology Oriented Synthesis. Institute of Electronic Design Automation, Technical University of Munish, 1996.
	5	A. Farrahi and M. Sarrafzadeh. Complexity of the Lookup- Table Minimization Problem for FPGA Technology Mapping. IEEE Trans. on Computer-Aided Design of Integrated Circuits And Systems, 13(11):1319-1332, 1994.
	6	Robert Francis , Jonathan Rose , Zvonko Vranesic, Chortle-crf: Fast technology mapping for lookup table-based FPGAs, Proceedings of the 28th conference on ACM/IEEE design automation, p.227-233, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127670]
	7	J. He and J. Rose. Technology Mapping for Heterogeneous FPGAs. In FPGA'92, 1994.
	8	Madhukar R. Korupolu , K. K. Lee , D. F. Wong, Exact tree-based FPGA technology mapping for logic blocks with independent LUTs, Proceedings of the 35th annual conference on Design automation, p.708-711, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277222]
	9	R. Murgai, N. Shenoy, R. K. Brayton, and A. Sangiovanni- Vincentelli. Improved Logic Synthesis Algorithms For Table Lookup Architectures. In IEEE International Conference on CAD, pages 564-567, 1991.
	10	Peichen Pan , Chih-Chang Lin, A new retiming-based technology mapping algorithm for LUT-based FPGAs, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.35-42, February 22-25, 1998, Monterey, California, United States [doi>10.1145/275107.275118]
	11	E. Sentovich, K. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. Stephan, R. Brayton, and A. Sangiovanni-Vincentelli. SIS: A System }or Sequential Circuit Synthesis. Electronics Research Laboratory, Memorandum No. UCB/ERL M92/41, 1992.
	12	Lucent Technologies. ORCA OR2C-A/ORsT-A Series FP- GAs Data Sheet. Lucent Technologies, Inc., Allentown, PA, 1996.
	13	Vantis and AMD Company. Vantis VF1 Field Programmable Gate Array. 1998.
	14	Bernd Wurth , Klaus Eckl , Kurt Antreich, Functional multiple-output decomposition: theory and an implicit algorithm, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.54-59, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217506]
	15	Xilinx. The Programmable Logic Data Book. Xilinx Inc., San Jose, CA, 1997.

CITED BY 41

	Jason Cong , Songjie Xu, Invited talk: synthesis challenges for next-generation high-performance and high-density PLDs, Proceedings of the 2000 conference on Asia South Pacific design automation, p.157-162, January 2000, Yokohama, Japan
	Gang Chen , Jason Cong, Simultaneous logic decomposition with technology mapping in FPGA designs, Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays, p.48-55, February 2001, Monterey, California, United States
	Jason Cong , Yean-Yow Hwang , Songjie Xu, Technology mapping for FPGAs with nonuniform pin delays and fast interconnections, Proceedings of the 36th ACM/IEEE conference on Design automation, p.373-378, June 21-25, 1999, New Orleans, Louisiana, United States
	Jason Cong , Hui Huang , Xin Yuan, Technology mapping for k/m-macrocell based FPGAs, Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, p.51-59, February 10-11, 2000, Monterey, California, United States
	Zhi-Hong Wang , En-Cheng Liu , Jianbang Lai , Ting-Chi Wang, Power minization in LUT-based FPGA technology mapping, Proceedings of the 2001 conference on Asia South Pacific design automation, p.635-640, January 2001, Yokohama, Japan
	Joey Y. Lin , Ashok Jagannathan , Jason Cong, Placement-driven technology mapping for LUT-based FPGAs, Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays, February 23-25, 2003, Monterey, California, USA
	Jason Cong , Kenneth Yan, Synthesis for FPGAs with embedded memory blocks, Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, p.75-82, February 10-11, 2000, Monterey, California, United States
	Alan Mishchenko , Satrajit Chatterjee , Robert Brayton, Improvements to technology mapping for LUT-based FPGAs, Proceedings of the internation symposium on Field programmable gate arrays, February 22-24, 2006, Monterey, California, USA
	Deming Chen , Jason Cong , Fei Li , Lei He, Low-power technology mapping for FPGA architectures with dual supply voltages, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, February 22-24, 2004, Monterey, California, USA
	Jason Cong , Yiping Fan , Guoling Han , Zhiru Zhang, Application-specific instruction generation for configurable processor architectures, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, February 22-24, 2004, Monterey, California, USA
	Jason Cong , Hui Huang, Depth optimal incremental mapping for field programmable gate arrays, Proceedings of the 37th conference on Design automation, p.290-293, June 05-09, 2000, Los Angeles, California, United States
	Chi-Chou Kao , Yen-Tai Lai, An efficient algorithm for finding the minimal-area FPGA technology mapping, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.10 n.1, p.168-186, January 2005
	Jason Cong , Hui Huang , Xin Yuan, Technology mapping and architecture evalution for k/m-macrocell-based FPGAs, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.10 n.1, p.3-23, January 2005
	Andrew Ling , Deshanand P. Singh , Stephen D. Brown, FPGA technology mapping: a study of optimality, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Andrew Ling , Deshanand P. Singh , Stephen D. Brown, FPGA technology mapping: a study of optimality, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Jason Cong , Kirill Minkovich, Optimality study of logic synthesis for LUT-based FPGAs, Proceedings of the internation symposium on Field programmable gate arrays, February 22-24, 2006, Monterey, California, USA
	Katherine Compton , Scott Hauck, Reconfigurable computing: a survey of systems and software, ACM Computing Surveys (CSUR), v.34 n.2, p.171-210, June 2002
	Yu Hu , Victor Shih , Rupak Majumdar , Lei He, FPGA area reduction by multi-output function based sequential resynthesis, Proceedings of the 45th annual conference on Design automation, June 08-13, 2008, Anaheim, California
	Quang Dinh , Deming Chen , Martin D. F. Wong, Efficient ASIP design for configurable processors with fine-grained resource sharing, Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays, February 24-26, 2008, Monterey, California, USA
	Joey Y. Lin , Deming Chen , Jason Cong, Optimal simultaneous mapping and clustering for FPGA delay optimization, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Donald Chai , Andreas Kuehlmann, Building a better Boolean matcher and symmetry detector, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Lei Cheng , Deming Chen , Martin D. F. Wong, GlitchMap: an FPGA technology mapper for low power considering glitches, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California
	Satrajit Chatterjee , Alan Mishchenko , Robert Brayton, Factor cuts, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
	Yu Hu , Victor Shih , Rupak Majumdar , Lei He, Exploiting symmetry in SAT-based Boolean matching for heterogeneous FPGA technology mapping, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
	Yu Hu , Satyaki Das , Steve Trimberger , Lei He, Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
	M. Teslenko , E. Dubrova, Hermes: LUT FPGA technology mapping algorithm for area minimization with optimum depth, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.748-751, November 07-11, 2004
	D. Chen , J. Cong, DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.752-759, November 07-11, 2004
	S. Chatterjee , A. Mishchenko , R. Brayton , X. Wang , T. Kam, Reducing structural bias in technology mapping, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.519-526, November 06-10, 2005, San Jose, CA
	Zile Wei , Donald Chai , A. Richard Newton , Andreas Kuehlmann, Fast Boolean Matching with Don't Cares, Proceedings of the 7th International Symposium on Quality Electronic Design, p.346-351, March 27-29, 2006
	Julien Lamoureux , Steven J. E. Wilton, On the Interaction Between Power-Aware FPGA CAD Algorithms, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.701, November 09-13, 2003
	Deming Chen , Jason Cong , Peichen Pan, FPGA Design Automation: A Survey, Foundations and Trends® in Electronic Design Automation, v.1 n.3, p.139-169, January 2006
	Stephen Jang , Billy Chan , Kevin Chung , Alan Mishchenko, WireMap: FPGA technology mapping for improved routability, Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays, February 24-26, 2008, Monterey, California, USA
	Alan Mishchenko , Sungmin Cho , Satrajit Chatterjee , Robert Brayton, Combinational and sequential mapping with priority cuts, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
	Kirill Minkovich , Jason Cong, Mapping for better than worst-case delays in LUT-based FPGA designs, Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays, February 24-26, 2008, Monterey, California, USA
	Andrew Kennings , Kristofer Vorwerk , Arun Kundu , Val Pevzner , Andy Fox, FPGA technology mapping with encoded libraries andstaged priority cuts, Proceeding of the ACM/SIGDA international symposium on Field programmable gate arrays, February 22-24, 2009, Monterey, California, USA
	Stephen Jang , Billy Chan , Kevin Chung , Alan Mishchenko, WireMap: FPGA Technology Mapping for Improved Routability and Enhanced LUT Merging, ACM Transactions on Reconfigurable Technology and Systems (TRETS), v.2 n.2, p.1-24, June 2009
	Alan Mishchenko , Robert Brayton , Satrajit Chatterjee, Boolean factoring and decomposition of logic networks, Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, November 10-13, 2008, San Jose, California
	Val Pevzner , Andrew Kennings , Andy Fox, Physical optimization for FPGAs using post-placement topology rewriting, Proceedings of the 2009 international symposium on Physical design, March 29-April 01, 2009, San Diego, California, USA
	Taiga Takata , Yusuke Matsunaga, An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs, Proceedings of the 19th ACM Great Lakes symposium on VLSI, May 10-12, 2009, Boston Area, MA, USA
	Hiroshi Shinohara , Hideaki Monji , Masahiro Iida , Toshinori Sueyoshi, A Novel Technique to Design Energy-Efficient Contexts for Reconfigurable Logic Devices, IEICE - Transactions on Information and Systems, v.E90-D n.12, p.1986-1989, December 2007
	Ion Bucur , Ioana Fagarasan , Cornel Popescu , Costin-Anton Boiangiu , George Culea, On K-LUT based FPGA optimum delay and optimal area mapping, Proceedings of the 10th WSEAS international conference on Mathematical and computational methods in science and engineering, p.137-142, November 07-09, 2008, Bucharest, Romania