A new high density and very low cost reprogrammable FPGA architecture

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A new high density and very low cost reprogrammable FPGA architecture

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International Symposium on Field Programmable Gate Arrays archive
Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays table of contents

Monterey, California, United States

Pages: 3 - 12

Year of Publication: 1999

ISBN:1-58113-088-0

Authors

Sinan Kaptanoglu	Actel Corporation, 955 East Arques Avenue, Sunnyvale CA
Greg Bakker	Actel Corporation, 955 East Arques Avenue, Sunnyvale CA
Arun Kundu	Actel Corporation, 955 East Arques Avenue, Sunnyvale CA
Ivan Corneillet	Actel Corporation, 955 East Arques Avenue, Sunnyvale CA
Ben Ting	BTR Inc., 20410 Town Center Lane. Suite 210, Cupertino CA

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 29, Citation Count: 3

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	J.S. Rose, R. J. Francis, D. M. Lewis, and P. Chow, IEEE Journal of Solid State Circuits, Vol. 25, No. 5, Oct. 1990, pp. 1217-1225.
	2	J. Kouloheris and A. E1-Gamal, ACM/SIGDA Workshop on FPGAs (FPGA '92), Feb. 1992, pp. 9-14.
	3	Stephen D. Brown , Robert J. Francis , Jonathan Rose , Zvonko G. Vranesic, Field-programmable gate arrays, Kluwer Academic Publishers, Norwell, MA, 1992
	4	Jason Cong , Songjie Xu, Delay-optimal technology mapping for FPGAs with heterogeneous LUTs, Proceedings of the 35th annual conference on Design automation, p.704-707, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277221]
	5	Jason Cong , Songjie Xu, Delay-oriented technology mapping for heterogeneous FPGAs with bounded resources, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.40-44, November 08-12, 1998, San Jose, California, United States [doi>10.1145/288548.288558]
	6	J. He and J. Rose, Custom Integrated Circuits Conference, May 1993, pp. 7.4.1-7.4.5.
	7	Vaughn Betz , Jonathan Rose, Using architectural “families” to increase FPGA speed and density, Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, p.10-16, February 12-14, 1995, Monterey, California, United States [doi>10.1145/201310.201312]
	8	A.A. Agarwal, and D. M. Lewis, ACM/SIGDA Workshop on FPGAs (FPGA '94), February 1994.

CITED BY 3

	Michael Hutton, Interconnect prediction for programmable logic devices, Proceedings of the 2001 international workshop on System-level interconnect prediction, p.125-131, March 31-April 01, 2001, Sonoma, California, United States
	Michael Hutton , Vinson Chan , Peter Kazarian , Victor Maruri , Tony Ngai , Jim Park , Rakesh Patel , Bruce Pedersen , Jay Schleicher , Sergey Shumarayev, Interconnect enhancements for a high-speed PLD architecture, Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays, February 24-26, 2002, Monterey, California, USA
	Elias Ahmed , Jonathan Rose, The effect of LUT and cluster size on deep-submicron FPGA performance and density, Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, p.3-12, February 10-11, 2000, Monterey, California, United States