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Variable length path branch prediction
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Source Architectural Support for Programming Languages and Operating Systems archive
Proceedings of the eighth international conference on Architectural support for programming languages and operating systems table of contents
San Jose, California, United States
Pages: 170 - 179  
Year of Publication: 1998
ISBN:1-58113-107-0
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Authors
Jared Stark  Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, Michigan
Marius Evers  Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, Michigan
Yale N. Patt  Department of Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, Michigan
Sponsors
SIGOPS: ACM Special Interest Group on Operating Systems
IEEE-CS : Computer Society
SIGARCH: ACM Special Interest Group on Computer Architecture
SIGPLAN: ACM Special Interest Group on Programming Languages
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 11,   Downloads (12 Months): 61,   Citation Count: 13
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ABSTRACT

Accurate branch prediction is required to achieve high performance in deeply pipelined, wide-issue processors. Recent studies have shown that conditional and indirect (or computed) branch targets can be accuratelypredicted by recording the path, which consists of the target addresses of recent branches, leading up to the branch. In current path based branch predictors, the N most recent target addresses are hashed together to form an index into a table, where N is some fixed integer. The indexed table entry isused to make a prediction for the current branch.This paper introduces a new branch predictor in which the value of N is allowed to vary. By constructing the index into the table using the last N target addresses, and using profiling information to select the proper value of N for each branch, extremely accurate branch prediction is achieved. For the SPECint95 gee benchmark, this new predictor has a conditional branch misprediction rate of 4.3% given a 4K byte hardware budget. For comparison, the gshare predictor, a predictor known for its high accuracy, has a conditional branch misprediction rate of 8.8% given the same hardware budget. For the indirect branches in gee, the new predictor achieves a misprediction rate of 27.7% when given a hardware budget of 512 bytes, whereas the best competingpredictor achieves a misprediction rate of 44.2% when given the same hardware budget.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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L. Gwennap, "Intel's MMX speeds multimedia," Microprocessor Report, March 1996.
 
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S. McFarling, "Combining branch predictors," Technical Report TN-36, Digital Western Research Laboratory, June 1993.
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CITED BY  13

Collaborative Colleagues:
Jared Stark: colleagues
Marius Evers: colleagues
Yale N. Patt: colleagues