Word-level decision diagrams, WLCDs and division

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Word-level decision diagrams, WLCDs and division

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International Conference on Computer Aided Design archive
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California, United States

Pages: 672 - 677

Year of Publication: 1998

ISBN:1-58113-008-2

Authors

Christoph Scholl	Institute of Computer Science, Albert-Ludwigs-University, D 79110 Freiburg im Breisgau, Germany
Bernd Becker	Institute of Computer Science, Albert-Ludwigs-University, D 79110 Freiburg im Breisgau, Germany
Thomas M. Weis	Institute of Computer Science, Albert-Ludwigs-University, D 79110 Freiburg im Breisgau, Germany

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 0, Downloads (12 Months): 3, Citation Count: 4

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	2	B. Beeker, R. Drechsler, and R. Enders. On the computational power of bit-level and word-level decision diagrams. InASP Design Automation Conf., pages 461--467, 1997.
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	7	Yirng-An Chen , Randal E. Bryant, PHDD: an efficient graph representation for floating point circuit verification, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.2-7, November 09-13, 1997, San Jose, California, United States
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	14	S. Malik, A.R. Wang, R.K. Brayton, and A.L. Sangiovanni- Vincentelli. Logic verification using binary decision diagrams in a logic synthesis environment. In Int'l Conf. on CAD, pages 6-9, 1988.
	15	M. N -akanishi. An exponential lower bound on the size of a binary moment diagram representing division. Master's thesis, Osaka University, 2 1998.
	16	Christoph Scholl, Word-Level Decision Diagrams, WLCDs and Division, Albert-Ludwigs University at Freiburg, 1998
	17	Stephan Waack, On the Descriptive and Algorithmic Power of Parity Ordered Binary Decision Diagrams, Proceedings of the 14th Annual Symposium on Theoretical Aspects of Computer Science, p.201-212, February 27-March 01, 1997

CITED BY 4

	Katarzyna Radecka , Zeljko Zilic, Design Verification by Test Vectors and Arithmetic Transform Universal Test Set, IEEE Transactions on Computers, v.53 n.5, p.628-640, May 2004
	Christoph Scholl , Bernd Becker , Thomas Weis, On WLCDs and the Complexity of Word-Level Decision Diagrams—A Lower Bound for Division, Formal Methods in System Design, v.20 n.3, p.311-326, May 2002
	R. Drechsler, Using Word-Level Information in Formal Hardware Verification, Automation and Remote Control, v.65 n.6, p.963-977, June 2004
	Stefan Höreth , Rolf Drechsler, Formal verification of word-level specifications, Proceedings of the conference on Design, automation and test in Europe, p.11-es, January 1999, Munich, Germany