Design of experiments in BDD variable ordering

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	1	Nevin Kapur , Debabrata Ghosh , Franc Brglez, Towards a new benchmarking paradigm in EDA: analysis of equivalence class mutant circuit distributions, Proceedings of the 1997 international symposium on Physical design, p.136-143, April 14-16, 1997, Napa Valley, California, United States [doi>10.1145/267665.267704]
	2	F. Brglez. Design of Experiments to Evaluate CAD Algorithms: Which Improvements Are Due to Improved Heuristic and Which Are Merely Due to Chance? Technical Report 1998-TR~CBL- 04-Brglez, CBL, CS Dept., NCSU, Box 7550, Raleigh, NC 27695, April 1998. Also available at http://uuu.~bl.ncsu.edu/- publicat ~ons/# 1998-TR~ CBL-04-Brglez.
	3	D. Ghosh , N. Kapur , J. Harlow, III , F. Brglez, Synthesis of wiring signature-invariant equivalence class circuit mutants and applications to benchmarking, Proceedings of the conference on Design, automation and test in Europe, p.656-663, February 23-26, 1998, Le Palais des Congrés de Paris, France
	4	J. E. Harlow and F. Brglez. Design of Experiments for Evaluation of BDD Packages Using Controlled Circuit Mutations. In Proceedings of the International Conference on Computer Aided Verification. Springer Verlag, Lecture Notes in Computer Science, November 1998. Also available from http://~, cbl.ncsu, edu/pablicat ions/#1998-FMeAD-Harlow.
	5	Richard Rudell, Dynamic variable ordering for ordered binary decision diagrams, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.42-47, November 07-11, 1993, Santa Clara, California, United States
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	7	Shipra Panda , Fabio Somenzi , Bernard F. Plessier, Symmetry detection and dynamic variable ordering of decision diagrams, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.628-631, November 06-10, 1994, San Jose, California, United States
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	9	F. Brglez and H. Fujiwara. Special Session on ATPG (Also introducing 'A Neutral Netlist of 10 Combinational Benchmark Circuits'). In Int. Syrup. On Circuits and Systems, 1985. Now a benchmark directory ISCAS85 at http://um~.ebl.ncsu.edulb enchmarks/Benclmarks -upto -1996. html.
	10	F. Somenzi. A Collection of BDD Variable Orders. Available from ftp: I/vlsi. colorado, edu/publorders, tar.gz, 1997.
	11	Robert K. Brayton , Gary D. Hachtel , Alberto L. Sangiovanni-Vincentelli , Fabio Somenzi , Adnan Aziz , Szu-Tsung Cheng , Stephen A. Edwards , Sunil P. Khatri , Yuji Kukimoto , Abelardo Pardo , Shaz Qadeer , Rajeev K. Ranjan , Shaker Sarwary , Thomas R. Shiple , Gitanjali Swamy , Tiziano Villa, VIS: A System for Verification and Synthesis, Proceedings of the 8th International Conference on Computer Aided Verification, p.428-432, August 03, 1996
	12	Pranav Ashar , Matthew Cheong, Efficient breadth-first manipulation of binary decision diagrams, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.622-627, November 06-10, 1994, San Jose, California, United States
	13	F. Somenzi et at. Colorado University Decision Diagram package (CUDD), release 2.1.2, 1997. Available from ftp://vlsi, colorado, e du/pub/cudd-2.1.2, tar. gz.
	14	D. E. Long. CMU BDD package, 1993. Available from hZtp://emc, cmu. edu/pub/b dd/bddlib, tar. Z.
	15	J. Calhoun and F. Brglez. A Framework and Method for Hierarchical Test Generation. IEEE Transactions on Computer-A~ded Design, 11(1):45-67, January 1992.
	16	A. Zemva , F. Brglez, Detectable perturbations: a paradigm for technology-specific multi-fault test generation, Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), p.350, April 30-May 03, 1995
	17	A. Zemva, F. Brglez, and B. Zajc. Multi-level Logic Optimization Based on Wave Synthesis of Permissible Mutation Functions (~,VASP). In International Workshop on Logic Synthesis (IWLS'98), June 1998. Also available from http://www, cbl. ncsu. edu/publications/#1998-IWLS-Zemva.