A simultaneous routing tree construction and fanout optimization algorithm

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A simultaneous routing tree construction and fanout optimization algorithm

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International Conference on Computer Aided Design archive
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California, United States

Pages: 625 - 630

Year of Publication: 1998

ISBN:1-58113-008-2

Authors

Amir H. Salek	Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA
Jinan Lou	Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA
Massoud Pedram	Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 6, Downloads (12 Months): 16, Citation Count: 16

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	LSP97	Jinan Lou , Amir H. Salek , Massoud Pedram, An exact solution to simultaneous technology mapping and linear placement problem, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.671-675, November 09-13, 1997, San Jose, California, United States
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	SLP98	Amir H. Salek , Jinan Lou , Massoud Pedram, A DSM design flow: putting floorplanning, technology-mapping, and gate-placement together, Proceedings of the 35th annual conference on Design automation, p.128-134, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277072]
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CITED BY 16

	Hai Zhou , D. F. Wong , I-Min Liu , Adnan Aziz, Simultaneous routing and buffer insertion with restrictions on buffer locations, Proceedings of the 36th ACM/IEEE conference on Design automation, p.96-99, June 21-25, 1999, New Orleans, Louisiana, United States
	Jiang Hu , Charles J. Alpert , Stephen T. Quay , Gopal Gandham, Buffer insertion with adaptive blockage avoidance, Proceedings of the 2002 international symposium on Physical design, April 07-10, 2002, San Diego, CA, USA
	Olivier Coudert, Logical and physical design: a flow perspective, Logic Synthesis and Verification, Kluwer Academic Publishers, Norwell, MA, 2001
	Jiang Hu , Sachin S. Sapatnekar, Simultaneous buffer insertion and non-Hanan optimization for VLSI interconnect under a higher order AWE model, Proceedings of the 1999 international symposium on Physical design, p.133-138, April 12-14, 1999, Monterey, California, United States
	Amir H. Ajami , Massoud Pedram, Post-layout timing-driven cell placement using an accurate net length model with movable Steiner points, Proceedings of the 2001 conference on Asia South Pacific design automation, p.595-600, January 2001, Yokohama, Japan
	Wei Chen , Cheng-Ta Hsieh , Massoud Pedram, Gate sizing with controlled displacement, Proceedings of the 1999 international symposium on Physical design, p.127-132, April 12-14, 1999, Monterey, California, United States
	Charles Alpert , Chris Chu , Gopal Gandham , Miloš Hrkić , Jiang Hu , Chandramouli Kashyap , Stephen Quay, Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique, Proceedings of the 2002 international symposium on Physical design, April 07-10, 2002, San Diego, CA, USA
	Amir H. Salek , Jinan Lou , Massoud Pedram, MERLIN: semi-order-independent hierarchical buffered routing tree generation using local neighborhood search, Proceedings of the 36th ACM/IEEE conference on Design automation, p.472-478, June 21-25, 1999, New Orleans, Louisiana, United States
	Rajeev Murgai, Technology-based transformations, Logic Synthesis and Verification, Kluwer Academic Publishers, Norwell, MA, 2001
	Olivier Coudert , Jason Cong , Sharad Malik , Majid Sarrafzadeh, Incremental CAD, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	Xiaoping Tang , Martin D. F. Wong, Tradeoff routing resource, runtime and quality in buffered routing, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.430-433, January 27-30, 2004, Yokohama, Japan
	Ankur Srivastava , Ryan Kastner , Chunhong Chen , Majid Sarrafzadeh, Timing driven gate duplication, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.1, p.42-51, January 2004
	Xiaoping Tang , Ruiqi Tian , Hua Xiang , D. F. Wong, A new algorithm for routing tree construction with buffer insertion and wire sizing under obstacle constraints, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	A. I. Erzin , J. D. Cho, Concurrent Placement and Routing in the Design of Integrated Circuits, Automation and Remote Control, v.64 n.12, p.1988-1999, December 2003
	D. Bañeres , J. Cortadella , M. Kishinevsky, Layout-aware gate duplication and buffer insertion, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
	Yibo Wang , Yici Cai , Xianlong Hong , Yi Zou, Stochastic Interconnect Tree Construction Algorithm with Accurate Delay and Power Consideration, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, v.E90-A n.5, p.1028-1037, May 2007