Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation

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Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation

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International Conference on Computer Aided Design archive
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California, United States

Pages: 617 - 624

Year of Publication: 1998

ISBN:1-58113-008-2

Authors

Chung-Ping Chen	Intel Corporation, 2111 N.E., 25th Ave. Hillsboro, OR and Department of Computer Sciences, University of Texas at Austin, Austin, TX
Chris C. N. Chu	Department of Computer Sciences, University of Texas at Austin, Austin, TX
D. F. Wong	Department of Computer Sciences, University of Texas at Austin, Austin, TX

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems

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ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 28, Citation Count: 27

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	3	Chung-Ping Chen and D. E Wong. A fast algorithm for optimal wire-sizing under Elmore delay model. In Proc. IEEE ISCAS, volume 4, pages 412-415, 1996.
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CITED BY 27

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	I-Min Liu , Adnan Aziz , D. F. Wong, Meeting delay constraints in DSM by minimal repeater insertion, Proceedings of the conference on Design, automation and test in Europe, p.436-440, March 27-30, 2000, Paris, France
	Tao Lin , Lawrence T. Pileggi, RC(L) interconnect sizing with second order considerations via posynomial programming, Proceedings of the 2001 international symposium on Physical design, p.16-21, April 01-04, 2001, Sonoma, California, United States
	Wei Chen , Cheng-Ta Hsieh , Massoud Pedram, Gate sizing with controlled displacement, Proceedings of the 1999 international symposium on Physical design, p.127-132, April 12-14, 1999, Monterey, California, United States
	Andrew R. Conn , Chandu Visweswariah, Overview of continuous optimization advances and applications to circuit tuning, Proceedings of the 2001 international symposium on Physical design, p.74-81, April 01-04, 2001, Sonoma, California, United States
	Vijay Sundararajan , Sachin S. Sapatnekar , Keshab K. Parhi, MINFLOTRANSIT: min-cost flow based transistor sizing tool, Proceedings of the 37th conference on Design automation, p.649-664, June 05-09, 2000, Los Angeles, California, United States
	Hui-Ru Jiang , Jing-Yang Jou , Yao-Wen Chang, Noise-constrained performance optimization by simultaneous gate and wire sizing based on Lagrangian relaxation, Proceedings of the 36th ACM/IEEE conference on Design automation, p.90-95, June 21-25, 1999, New Orleans, Louisiana, United States
	Noriyuki Miura , Naoki Kato , Tadahiro Kuroda, Practical methodology of post-layout gate sizing for 15% more power saving, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.434-437, January 27-30, 2004, Yokohama, Japan
	Chandu Visweswariah , Andrew R. Conn, Formulation of static circuit optimization with reduced size, degeneracy and redundancy by timing graph manipulation, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.244-252, November 07-11, 1999, San Jose, California, United States
	Jeng-Liang Tsai , Tsung-Hao Chen , Charlie Chung-Ping Chen, Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA
	Tai-Chen Chen , Song-Ra Pan , Yao-Wen Chang, Timing modeling and optimization under the transmission line model, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.1, p.28-41, January 2004
	Hiran Tennakoon , Carl Sechen, Efficient and accurate gate sizing with piecewise convex delay models, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Hiran Tennakoon , Carl Sechen, Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.395-402, November 10-14, 2002, San Jose, California
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	Min Ni , Seda Ogrenci Memik, Self-heating-aware optimal wire sizing under Elmore delay model, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
	I-Jye Lin , Tsui-Yee Ling , Yao-Wen Chang, Statistical circuit optimization considering device andinterconnect process variations, Proceedings of the 2007 international workshop on System level interconnect prediction, March 17-18, 2007, Austin, Texas, USA
	Osama Neiroukh , Xiaoyu Song, Improving the Process-Variation Tolerance of Digital Circuits Using Gate Sizing and Statistical Techniques, Proceedings of the conference on Design, Automation and Test in Europe, p.294-299, March 07-11, 2005
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