Multiway partitioning with pairwise movement

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Multiway partitioning with pairwise movement

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International Conference on Computer Aided Design archive
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California, United States

Pages: 512 - 516

Year of Publication: 1998

ISBN:1-58113-008-2

Authors

Jason Cong	UCLA Depmtment of Computer Science, Los Angeles, CA
Sung Kyu Lim	UCLA Depmtment of Computer Science, Los Angeles, CA

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 19, Citation Count: 19

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Charles J. Alpert, The ISPD98 circuit benchmark suite, Proceedings of the 1998 international symposium on Physical design, p.80-85, April 06-08, 1998, Monterey, California, United States [doi>10.1145/274535.274546]
	2	C. J. Alpert , A. B. Kahng, Multi-way partitioning via spacefilling curves and dynamic programming, Proceedings of the 31st annual conference on Design automation, p.652-657, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196603]
	3	Pak K. Chan , Martine D. F. Schlag , Jason Y. Zien, Spectral K-way ratio-cut partitioning and clustering, Proceedings of the 30th international conference on Design automation, p.749-754, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.165117]
	4	J. Cong, W. Labio, and N. Shivakumar. Multi-way VLSI circuit partitioning based on dual net representation. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pages 396-409, 1996.
	5	Jason Cong , Honching Peter Li , Sung Kyu Lim , Toshiyuki Shibuya , Dongmin Xu, Large scale circuit partitioning with loose/stable net removal and signal flow based clustering, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.441-446, November 09-13, 1997, San Jose, California, United States
	6	J. Cong and S. K. Lim. Multiway partitioning with pairwise movement. Technical Report 980029, CS Dept. of UCLA, Aug. 1998.
	7	C. M. Fiduccia , R. M. Mattheyses, A linear-time heuristic for improving network partitions, Proceedings of the 19th conference on Design automation, p.175-181, January 1982
	8	G. Karypis and V. Kumar. Multilevel k-way partitioning scheme for irregular graphs. Techmcal Report 95- 064, CS Dept. of Univ. of Minnesota, 1995.
	9	B. Kernighan and S. Lin. An efficient heuristic procedure for partitioning of electrical circuits. Bell System Technical Journal, pages 291-307, 1970.
	10	L. A. Sanchis, Multiple-Way Network Partitioning, IEEE Transactions on Computers, v.38 n.1, p.62-81, January 1989 [doi>10.1109/12.8730]
	11	Laura A. Sanchis, Multiple-Way Network Partitioning with Different Cost Functions, IEEE Transactions on Computers, v.42 n.12, p.1500-1504, December 1993 [doi>10.1109/12.260640]
	12	Ching-Wei Yeh , Chung-Kuan Cheng , Ting-Ting Y. Lin, A general purpose multiple way partitioning algorithm, Proceedings of the 28th conference on ACM/IEEE design automation, p.421-426, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127706]

CITED BY 19

	Maogang Wang , Majid Sarrafzadeh, On the behavior of congestion minimization during placement, Proceedings of the 1999 international symposium on Physical design, p.145-150, April 12-14, 1999, Monterey, California, United States
	Jason Cong , Michail Romesis , Min Xie, Optimality, scalability and stability study of partitioning and placement algorithms, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA
	George Karypis , Vipin Kumar, Multilevel k-way hypergraph partitioning, Proceedings of the 36th ACM/IEEE conference on Design automation, p.343-348, June 21-25, 1999, New Orleans, Louisiana, United States
	Jason Cong , Sung Kyu Lim , Chang Wu, Performance driven multi-level and multiway partitioning with retiming, Proceedings of the 37th conference on Design automation, p.274-279, June 05-09, 2000, Los Angeles, California, United States
	Jason Cong , Sung Kyu Lim, Performance driven multiway partitioning, Proceedings of the 2000 conference on Asia South Pacific design automation, p.441-446, January 2000, Yokohama, Japan
	Jason Cong , Majid Sarrafzadeh, Incremental physical design, Proceedings of the 2000 international symposium on Physical design, p.84-92, May 2000, San Diego, California, United States
	Patrick H. Madden, Partitioning by iterative deletion, Proceedings of the 1999 international symposium on Physical design, p.83-89, April 12-14, 1999, Monterey, California, United States
	Jason Cong , Sung Kyu Lim, Edge separability based circuit clustering with application to circuit partitioning, Proceedings of the 2000 conference on Asia South Pacific design automation, p.429-434, January 2000, Yokohama, Japan
	Sheldon X.-D. Tan , C.-J. Richard Shi, Balanced multi-level multi-way partitioning of analog integrated circuits for hierarchical symbolic analysis, Integration, the VLSI Journal, v.34 n.1-2, p.65-86, May 2003
	Michael Hutton , Khosrow Adibsamii , Andrew Leaver, Adaptive delay estimation for partitioning-driven PLD placement, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.1, p.60-63, February 2003
	Andrew E. Caldwell , Andrew B. Kahng , Igor L. Markov, Design and implementation of move-based heuristics for VLSI hypergraph partitioning, Journal of Experimental Algorithmics (JEA), 5, p.5-es, 2000
	Maogang Wang , Sung Lim , Jason Cong , Majid Sarrafzadeh, Multi-way partitioning using bi-partition heuristics, Proceedings of the 2000 conference on Asia South Pacific design automation, p.667, January 2000, Yokohama, Japan
	Mongkol Ekpanyapong , Sung Kyu Lim, Performance-driven global placement via adaptive network characterization, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.137-142, January 27-30, 2004, Yokohama, Japan
	Chun Che Fung , Jia Bin Li , Kok Wai Wong , Kit Po Wang, A Java-based parallel platform for the implementation of evolutionary computation for engineering applications, International Journal of Systems Science, v.35 n.13-14, p.741-750, 20 October 2004
	Yong-Hyuk Kim , Yourim Yoon , Alberto Moraglio , Byung-Ro Moon, Geometric crossover for multiway graph partitioning, Proceedings of the 8th annual conference on Genetic and evolutionary computation, July 08-12, 2006, Seattle, Washington, USA
	Alberto Moraglio , Yong-Hyuk Kim , Yourim Yoon , Byung-Ro Moon, Geometric crossovers for multiway graph partitioning, Evolutionary Computation, v.15 n.4, p.445-474, Winter 2007
	Aleksandar Trifunović , William J. Knottenbelt, Parallel multilevel algorithms for hypergraph partitioning, Journal of Parallel and Distributed Computing, v.68 n.5, p.563-581, May, 2008
	Lijun Li , Carl Tropper, A Multiway Design-driven Partitioning Algorithm for Distributed Verilog Simulation, Simulation, v.85 n.4, p.257-270, April 2009
	Navaratnasothie Selvakkumaran , George Karypis, Multi.Objective Hypergraph Partitioning Algorithms for Cut and Maximum Subdomain Degree Minimization, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.726, November 09-13, 2003