Network flow based circuit partitioning for time-multiplexed FPGAs

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Network flow based circuit partitioning for time-multiplexed FPGAs

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International Conference on Computer Aided Design archive
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California, United States

Pages: 497 - 504

Year of Publication: 1998

ISBN:1-58113-008-2

Authors

Huiqun Liu	Department of Computer Sciences, University of Texas at Austin, TX
D. F. Wong	Department of Computer Sciences, University of Texas at Austin, TX

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 18, Citation Count: 13

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Steve Trimberger, Scheduling designs into a time-multiplexed FPGA, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.153-160, February 22-25, 1998, Monterey, California, United States [doi>10.1145/275107.275135]
	2	Douglas Chang , Malgorzata Marek-Sadowska, Partitioning sequential circuits on dynamically reconfiguable FPGAs, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.161-167, February 22-25, 1998, Monterey, California, United States [doi>10.1145/275107.275136]
	3	Douglas Chang , Malgorzata Marek-Sadowska, Buffer minimization and time-multiplexed I/O on dynamically reconfigurable FPGAs, Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, p.142-148, February 09-11, 1997, Monterey, California, United States [doi>10.1145/258305.258331]
	4	Sasan Iman, Massoud Pedram, Charles Fabian and Jason Cong, "Finding Uni-Directional Cuts Based on Physical Partitioning and Logic Restructuring", 4th International Workshop on Physical Design, 1993.
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	13	Michael R. Garey , David S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness, W. H. Freeman & Co., New York, NY, 1979
	14	C. M. Fiduccia , R. M. Mattheyses, A linear-time heuristic for improving network partitions, Proceedings of the 19th conference on Design automation, p.175-181, January 1982
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	16	Honghua Yang , D. F. Wong, Efficient network flow based min-cut balanced partitioning, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.50-55, November 06-10, 1994, San Jose, California, United States
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CITED BY 13

	Eric S. H. Wong , Evangeline F. Y. Young , W. K. Mak, Clustering based acyclic multi-way partitioning, Proceedings of the 13th ACM Great Lakes symposium on VLSI, April 28-29, 2003, Washington, D. C., USA
	Mango Chia-Tso Chao , Guang-Ming Wu , Iris Hui-Ru Jiang , Yao-Wen Chang, A clustering- and probability-based approach for time-multiplexed FPGA partitioning, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.364-369, November 07-11, 1999, San Jose, California, United States
	Huiqun Liu , D. F. Wong, Circuit partitioning for dynamically reconfigurable FPGAs, Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, p.187-194, February 21-23, 1999, Monterey, California, United States
	Huiqun Liu , D. F. Wong, A graph theoretic optimal algorithm for schedule compression in time-multiplexed FPGA partitioning, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.400-405, November 07-11, 1999, San Jose, California, United States
	Min Zhao , Sachin S. Sapatnekar, Timing-driven partitioning for two-phase domino and mixed static/domino implementations, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.107-110, November 07-11, 1999, San Jose, California, United States
	Daler N. Rakhmatov , Sarma B. K. Vrudhula, Hardware-software bipartitioning for dynamically reconfigurable systems, Proceedings of the tenth international symposium on Hardware/software codesign, May 06-08, 2002, Estes Park, Colorado
	Wai-Kei Mak , Evangeline F. Y. Young, Temporal logic replication for dynamically reconfigurable FPGA partitioning, Proceedings of the 2002 international symposium on Physical design, April 07-10, 2002, San Diego, CA, USA
	Andre DeHon , Michael J. Wilson, Nanowire-based sublithographic programmable logic arrays, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, February 22-24, 2004, Monterey, California, USA
	Guang-Ming Wu , Jai-Ming Lin , Yao-Wen Chang, Performance-driven placement for dynamically reconfigurable FPGAs, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.7 n.4, p.628-642, October 2002
	Soheil Ghiasi , Ani Nahapetian , Majid Sarrafzadeh, An optimal algorithm for minimizing run-time reconfiguration delay, ACM Transactions on Embedded Computing Systems (TECS), v.3 n.2, p.237-256, May 2004
	Guang-Ming Wu , Mango Chia-Tso Chao , Yao-Wen Chang, A clustering- and probability-based approach for time-multiplexed FPGA partitioning, Integration, the VLSI Journal, v.38 n.2, p.245-265, December 2004
	Yung-Chuan Jiang , Jhing-Fa Wang, Temporal partitioning data flow graphs for dynamically reconfigurable computing, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.12, p.1351-1361, December 2007
	Abdellatif Mtibaa , Bouraoui Ouni , Mohamed Abid, An efficient list scheduling algorithm for time placement problem, Computers and Electrical Engineering, v.33 n.4, p.285-298, July, 2007