Static power optimization of deep submicron CMOS circuits for dual VT technology

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Static power optimization of deep submicron CMOS circuits for dual VT technology

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International Conference on Computer Aided Design archive
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California, United States

Pages: 490 - 496

Year of Publication: 1998

ISBN:1-58113-008-2

Authors

Qi Wang	Center for Low Power Electronics, ECE Department, University of Arizona, Tucson, AZ
Sarma B. K. Vrudhula	Center for Low Power Electronics, ECE Department, University of Arizona, Tucson, AZ

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 30, Citation Count: 22

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 22

	Ki-Wook Kim , Seong-Ook Jung , Prashant Saxena , C. L. Liu , Sung-Mo Kang, Coupling delay optimization by temporal decorrelation using dual threshold voltage technique, Proceedings of the 38th conference on Design automation, p.732-737, June 2001, Las Vegas, Nevada, United States
	S. Naidu , E. Jacobs, Minimizing stand-by leakage power in static CMOS circuits, Proceedings of the conference on Design, automation and test in Europe, p.370-376, March 2001, Munich, Germany
	J. Adam Butts , Gurindar S. Sohi, A static power model for architects, Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture, p.191-201, December 2000, Monterey, California, United States
	Masayuki Hirabayashi , Koichi Nose , Takayasu Sakurai, Design methodology and optimization strategy for dual-VTH scheme using commercially available tools, Proceedings of the 2001 international symposium on Low power electronics and design, p.283-286, August 2001, Huntington Beach, California, United States
	Tanay Karnik , Yibin Ye , James Tschanz , Liqiong Wei , Steven Burns , Venkatesh Govindarajulu , Vivek De , Shekhar Borkar, Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Supamas Sirichotiyakul , Tim Edwards , Chanhee Oh , Rajendran Panda , David Blaauw, Duet: an accurate leakage estimation and optimization tool for dual-V_t circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.2, p.79-90, April 2002
	Supamas Sirichotiyakul , Tim Edwards , Chanhee Oh , Jingyan Zuo , Abhijit Dharchoudhury , Rajendran Panda , David Blaauw, Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing, Proceedings of the 36th ACM/IEEE conference on Design automation, p.436-441, June 21-25, 1999, New Orleans, Louisiana, United States
	Liqiong Wei , Zhanping Chen , Kaushik Roy , Yibin Ye , Vivek De, Mixed-Vth (MVT) CMOS circuit design methodology for low power applications, Proceedings of the 36th ACM/IEEE conference on Design automation, p.430-435, June 21-25, 1999, New Orleans, Louisiana, United States
	Tyler Thorp , Gin Yee , Carl Sechen, Monotonic static CMOS and dual-VT technology, Proceedings of the 1999 international symposium on Low power electronics and design, p.151-155, August 16-17, 1999, San Diego, California, United States
	David Nguyen , Abhijit Davare , Michael Orshansky , David Chinnery , Brandon Thompson , Kurt Keutzer, Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	Mahesh Ketkar , Sachin S. Sapatnekar, Standby power optimization via transistor sizing and dual threshold voltage assignment, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.375-378, November 10-14, 2002, San Jose, California
	Ankur Srivastava, Simultaneous Vt selection and assignment for leakage optimization, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	Ki-Wook Kim , Seong-Ook Jung , Taewhan Kim , Prashant Saxena , C. L. Liu , Sung-Mo Kang, Coupling delay optimization by temporal decorrelation using dual threshold voltage technique, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.5, p.879-887, October 2003
	Nikhil Jayakumar , Sunil P. Khatri, An ASIC design methodology with predictably low leakage, using leakage-immune standard cells, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	Narender Hanchate , Nagarajan Ranganathan, LECTOR: a technique for leakage reduction in CMOS circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.2, p.196-205, February 2004
	Keoncheol Shin , Taewhan Kim, Leakage power minimization for the synthesis of parallel multiplier circuits, Proceedings of the 14th ACM Great Lakes symposium on VLSI, April 26-28, 2004, Boston, MA, USA
	Ashish Srivastava , Dennis Sylvester , David Blaauw, Statistical optimization of leakage power considering process variations using dual-Vth and sizing, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Rajeev Rao , Ashish Srivastava , David Blaauw , Dennis Sylvester, Statistical analysis of subthreshold leakage current for VLSI circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.2, p.131-139, February 2004
	Azadeh Davoodi , Ankur Srivastava, Probabilistic dual-Vth leakage optimization under variability, Proceedings of the 2005 international symposium on Low power electronics and design, August 08-10, 2005, San Diego, CA, USA
	Murari Mani , Anirudh Devgan , Michael Orshansky, An efficient algorithm for statistical minimization of total power under timing yield constraints, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Nikhil Jayakumar , Sunil P. Khatri, A predictably low-leakage ASIC design style, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.3, p.276-285, March 2007
	A. K. Singh , M. Mani , M. Orshansky, Statistical technology mapping for parametric yield, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.511-518, November 06-10, 2005, San Jose, CA