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Node sampling: a robust RTL power modeling approach

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International Conference on Computer Aided Design archive
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California, United States

Pages: 461 - 467

Year of Publication: 1998

ISBN:1-58113-008-2

Authors

Alessandro Bogliolo	DEIS - Università di Bologna - Italy
Luca Benini	DEIS - Università di Bologna - Italy

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 0, Downloads (12 Months): 1, Citation Count: 8

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	S. PoweU and E Chau, "Estimating power dissipation of VLSI signal processing chips: the PFA techniques" in Proc. of Workshop on VLSI Sig. Proc., pp. 250-259,1990.
	2	Huzefa Mehta , Robert Michael Owens , Mary Jane Irwin, Energy characterization based on clustering, Proceedings of the 33rd annual conference on Design automation, p.702-707, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240651]
	3	Qinru Qiu , Qing Wu , Massoud Pedram , Chih-Shun Ding, Cycle-accurate macro-models for RT-level power analysis, Proceedings of the 1997 international symposium on Low power electronics and design, p.125-130, August 18-20, 1997, Monterey, California, United States [doi>10.1145/263272.263305]
	4	Cheng-Ta Hsieh , Qing Wu , Chih-Shun Ding , Massoud Pedram, Statistical sampling and regression analysis for RT-level power evaluation, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.583-588, November 10-14, 1996, San Jose, California, United States
	5	Subodh Gupta , Farid N. Najm, Power macromodeling for high level power estimation, Proceedings of the 34th annual conference on Design automation, p.365-370, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266171]
	6	L. Benini, A. Bogliolo, M. Favalli, and G. De Micheli, "Regression models for behavioral power estimation," in Proc. of PATMOS, pp. 179-I 87,1996.
	7	A. Bogliolo , L. Benini , G. De Micheli, Adaptive least mean square behavioral power modeling, Proceedings of the 1997 European conference on Design and Test, p.404, March 17-20, 1997
	8	S. Yang, "Logic Synthesis and Optimization Benchmarks User Guide Version 3.0,' Technical report, Microelectronics Center of North Carolina, Research Triangle Park, NC, January 199 I.
	9	Kishar Shridharbhai Trivedi, Probability and Statistics with Reliability, Queuing and Computer Science Applications, Prentice Hall PTR, Upper Saddle River, NJ, 1982
	10	Ellen Sentovich , Kanwar Jit Singh , Cho W. Moon , Hamid Savoj , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli, Sequential Circuit Design Using Synthesis and Optimization, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.328-333, October 11-14, 1992
	11	L. Benini and M. Favalli and B. Riccb, "Analysis of hazard contribution to power dissipation in CMOS IC's" in Proc. oflnt.l libr'kshop on Low Power Design, pp. 27-32, 1994.

CITED BY 8

	Heng-Liang Huang , Jiing-Yuan Lin , Wen-Zen Shen , Jing-Yang Jou, A new method for constructing IP level power model based on power sensitivity, Proceedings of the 2000 conference on Asia South Pacific design automation, p.135-140, January 2000, Yokohama, Japan
	Alessandro Bogliolo , Roberto Corgnati , Enrico Macii , Massimo Poncino, Parameterized RTL power models for combinational soft macros, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.284-288, November 07-11, 1999, San Jose, California, United States
	Srinivas Bodapati , Farid Najm, Frequency-domain supply current macro-model, Proceedings of the 2001 international symposium on Low power electronics and design, p.295-298, August 2001, Huntington Beach, California, United States
	Srinivas Bodapati , Farid N. Najm, High-level current macro-model for power-grid analysis, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Subodh Gupta , Farid N. Najm, Energy-per-cycle estimation at RTL, Proceedings of the 1999 international symposium on Low power electronics and design, p.121-126, August 16-17, 1999, San Diego, California, United States
	Subodh Gupta , Farid N. Najm, Energy and peak-current per-cycle estimation at RTL, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.4, p.525-537, August 2003
	B. Alorda , V. Canals , J. Segura, A Two-Level Power-Grid Model for Transient Current Testing Evaluation, Journal of Electronic Testing: Theory and Applications, v.20 n.5, p.543-552, October 2004
	Lin Zhong , S. Ravi , A. Raghunathan , N. K. Jha, Power estimation for cycle-accurate functional descriptions of hardware, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.668-675, November 07-11, 2004