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Communication synthesis for distributed embedded systems
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Source International Conference on Computer Aided Design archive
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design table of contents
San Jose, California, United States
Pages: 437 - 444  
Year of Publication: 1998
ISBN:1-58113-008-2
Authors
Ross B. Ortega  Dept. of Computing and Software Systems, University of Washington, Bothell, WA
Gaetano Borriello  Dept. of Computer Science & Engineering, University of Washington, Bothell, WA
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 9,   Downloads (12 Months): 37,   Citation Count: 35
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Pai Chou , Ross Ortega , Gaetano Borriello, Synthesis fo the hardware/software interface in microcontroller-based systems, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.488-495, November 1992, Santa Clara, California, United States
 
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Pai Chou , Ross B. Ortega , Gaetano Borriello, Interface co-synthesis techniques for embedded systems, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.280-287, November 05-09, 1995, San Jose, California, United States
 
5
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Daniel D. Gajski , Frank Vahid , Sanjiv Narayan , Jie Gong, Specification and design of embedded systems, Prentice-Hall, Inc., Upper Saddle River, NJ, 1994
 
8
Michael Gasteier , Manfred Glesner, Bus-Based Communication Synthesis on System-Level, Proceedings of the 9th international symposium on System synthesis, p.65, November 06-08, 1996
9
Ken Hines , Gaetano Borriello, Dynamic communication models in embedded system co-simulation, Proceedings of the 34th annual conference on Design automation, p.395-400, June 09-13, 1997, Anaheim, California, United States  [doi>10.1145/266021.266178]
 
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13
Ross B. Ortega , Luciano Lavagno , Gaetano Borriello, Models and methods for HW/SW intellectual property interfacing, System-level synthesis, Kluwer Academic Publishers, Norwell, MA, 1999
 
14
Ross B. Ortega , Gaetano Borriello, Communication Synthesis for Embedded Systems with Global Considerations, Proceedings of the 5th International Workshop on Hardware/Software Co-Design, p.69, March 24-26, 1997
 
15
I2C Peripherals for Microcontrollers. Philips Semiconductors, 1992.
 
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Bran Selic , Garth Gullekson , Paul T. Ward, Real-time object-oriented modeling, John Wiley & Sons, Inc., New York, NY, 1994
 
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K. Tindell and A. Bums. Guaranteed message latencies for distributed safety-critical hard real-time control networks. Technical Report YCS-94-229, University of York, 1994.
 
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B.P. Upender and P.J. Koopman Jr. Communication protocols for embedded systems. Embedded Systems Programming, 7(11):46-58, November 1994.
 
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Frank Vahid , Linus Tauro, An Object-Oriented Communication Library for Hardware-Software CoDesign, Proceedings of the 5th International Workshop on Hardware/Software Co-Design, p.81, March 24-26, 1997
 
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CITED BY  35
Neal K. Tibrewala , JoAnn M. Paul , Donald E. Thomas, Modeling and evaluation of hardware/software designs, Proceedings of the ninth international symposium on Hardware/software codesign, p.11-16, April 2001, Copenhagen, Denmark
Gaetano Borriello , Luciano Lavagno , Ross B. Ortega, Interface synthesis: a vertical slice from digital logic to software components, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.693-695, November 08-12, 1998, San Jose, California, United States
Jinfeng Liu , Pai H. Chou , Nader Bagherzadeh, Combined functional partitioning and communication speed selection for networked voltage-scalable processors, Proceedings of the 15th international symposium on System Synthesis, October 02-04, 2002, Kyoto, Japan
JoAnn M. Paul , Arne J. Suppé , Donald E. Thomas, Modeling and simulation of steady state and transient behaviors for emergent SoCs, Proceedings of the 14th international symposium on Systems synthesis, September 30-October 03, 2001, Montréal, P.Q., Canada
Kanishka Lahiri , Anand Raghunathan , Ganesh Lakshminarayana , Sujit Dey, Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips, Proceedings of the 37th conference on Design automation, p.513-518, June 05-09, 2000, Los Angeles, California, United States
Paul Pop , Petru Eles , Traian Pop , Zebo Peng, An approach to incremental design of distributed embedded systems, Proceedings of the 38th conference on Design automation, p.450-455, June 2001, Las Vegas, Nevada, United States
P. Coste , F. Hessel , Ph. Le Marrec , Z. Sugar , M. Romdhani , R. Suescun , N. Zergainoh , A. A. Jarraya, Multilanguage design of heterogeneous systems, Proceedings of the seventh international workshop on Hardware/software codesign, p.54-58, March 1999, Rome, Italy
Faraydon Karim , Anh Nguyen , Sujit Dey , Ramesh Rao, On-chip communication architecture for OC-768 network processors, Proceedings of the 38th conference on Design automation, p.678-683, June 2001, Las Vegas, Nevada, United States
Paul Pop , Petru Eles , Zebo Peng, Bus access optimization for distributed embedded systems based on schedulability analysis, Proceedings of the conference on Design, automation and test in Europe, p.567-575, March 27-30, 2000, Paris, France
C. Rust , F. Stappert , P. Altenbernd , J. Tacken, From high-level specifications down to software implementations of parallel embedded real-time systems, Proceedings of the conference on Design, automation and test in Europe, p.686-691, March 27-30, 2000, Paris, France
Paul Pop , Petru Eles , Traian Pop , Zebo Peng, Minimizing system modification in an incremental design approach, Proceedings of the ninth international symposium on Hardware/software codesign, p.183-188, April 2001, Copenhagen, Denmark
JoAnn M. Paul , Simon N. Peffers , Donald E. Thomas, A codesign virtual machine for hierarchical, balanced hardware/software system modeling, Proceedings of the 37th conference on Design automation, p.390-395, June 05-09, 2000, Los Angeles, California, United States
Jinfeng Liu , Pai H. Chou , Nader Bagherzadeh, Communication speed selection for embedded systems with networked voltage-scalable processors, Proceedings of the tenth international symposium on Hardware/software codesign, May 06-08, 2002, Estes Park, Colorado
Michael Franz, A fresh look at low-power mobile computing, Compilers and operating systems for low power, Kluwer Academic Publishers, Norwell, MA, 2003
Paul Pop , Petru Eles , Zebo Peng, Schedulability-Driven Communication Synthesis for Time Triggered Embedded Systems, Real-Time Systems, v.26 n.3, p.297-325, April 2004
Paul Pop , Petru Eles , Zebo Peng , Traian Pop, Scheduling and mapping in an incremental design methodology for distributed real-time embedded systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.8, p.793-811, August 2004
Kanishka Lahiri , Anand Raghunathan , Sujit Dey, Efficient exploration of the SoC communication architecture design space, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
Sungchan Kim , Chaeseok Im , Soonhoi Ha, Schedule-aware performance estimation of communication architecture for efficient design space exploration, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.13 n.5, p.539-552, May 2005
Faraydon Karim , Anh Nguyen , Sujit Dey, An Interconnect Architecture for Networking Systems on Chips, IEEE Micro, v.22 n.5, p.36-45, September 2002
Sujan Pandey , Manfred Glesner , Max Mühlhäuser, Performance aware on-chip communication synthesis and optimization for shared multi-bus based architecture, Proceedings of the 18th annual symposium on Integrated circuits and system design, September 04-07, 2005, Florianolpolis, Brazil
Matthias Gries, Methods for evaluating and covering the design space during early design development, Integration, the VLSI Journal, v.38 n.2, p.131-183, December 2004
Dongwan Shin , Samar Abdi , Daniel D. Gajski, Automatic generation of bus functional models from transaction level models, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.756-758, January 27-30, 2004, Yokohama, Japan
Nattawut Thepayasuwan , Alex Doboli, Layout conscious approach and bus architecture synthesis for hardware/software codesign of systems on chip optimized for speed, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.13 n.5, p.525-538, May 2005
Trevor Meyerowitz , Claudio Pinello , Alberto Sangiovanni-Vincentelli, A tool for describing and evaluating hierarchical real-time bus scheduling policies, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
Dongwan Shin , Andreas Gerstlauer , Rainer Dömer , Daniel D. Gajski, Automatic network generation for system-on-chip communication design, Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 19-21, 2005, Jersey City, NJ, USA
Sudeep Pasricha , Nikil Dutt , Mohamed Ben-Romdhane, Automated throughput-driven synthesis of bus-based communication architectures, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
Sujan Pandey , Manfred Glesner, Simultaneous on-chip bus synthesis and voltage scaling under random on-chip data traffic, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.10, p.1111-1124, October 2007
Pai Chou , Ross Ortega , Ken Hines , Kurt Patridge , Gaetano Borriello, ipChinook: an integrated IP-based design framework for distributed embedded systems, Proceedings of the 36th ACM/IEEE conference on Design automation, p.44-49, June 21-25, 1999, New Orleans, Louisiana, United States
Dongwan Shin , Andreas Gerstlauer , Junyu Peng , Rainer Dömer , Daniel D. Gajski, Automatic generation of transaction level models for rapid design space exploration, Proceedings of the 4th international conference on Hardware/software codesign and system synthesis, October 22-25, 2006, Seoul, Korea
Alessandro Pinto , Alvise Bonivento , Allberto L. Sangiovanni-Vincentelli , Roberto Passerone , Marco Sgroi, System level design paradigms: Platform-based design and communication synthesis, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.11 n.3, p.537-563, July 2006
Sankalp Kallakuri , Alex Doboli , Simona Doboli, Applying stochastic modeling to bus arbitration for systems-on-chip, Integration, the VLSI Journal, v.40 n.2, p.183-191, February, 2007
Youngchul Cho , Ganghee Lee , Sungjoo Yoo , Kiyoung Choi , Nacer-Eddine Zergainoh, Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design, Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum, p.20132, March 03-07, 2003
Nattawut Thepayasuwan , Alex Doboli, Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on Chip, Proceedings of the conference on Design, automation and test in Europe, p.10108, February 16-20, 2004
Robertas Damaševičius , Vytautas Štuikys, Wrapping of Soft IPs for Interface-based Design Using Heterogeneous Metaprogramming, Informatica, v.14 n.1, p.3-18, January 2003
Krishna Sekar , Kanishka Lahiri , Anand Raghunathan , Sujit Dey, Dynamically configurable bus topologies for high-performance on-chip communication, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.16 n.10, p.1413-1426, October 2008

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.3 SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS
      Subjects: Real-time and embedded systems

Additional Classification:
  C. Computer Systems Organization
  C.2 COMPUTER-COMMUNICATION NETWORKS

  G. Mathematics of Computing
  G.4 MATHEMATICAL SOFTWARE
      Subjects: Algorithm design and analysis

  J. Computer Applications


General Terms:
Algorithms, Design, Performance, Standardization, Theory


Keywords:
bus protocols, communication synthesis, distributed heterogeneous embedded systems, hardware/software co-synthesis, interprocessor communication, multihop communication

Collaborative Colleagues:
Ross B. Ortega: colleagues
Gaetano Borriello: colleagues

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