Hardware/software co-synthesis with memory hierarchies

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Hardware/software co-synthesis with memory hierarchies

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International Conference on Computer Aided Design archive
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California, United States

Pages: 430 - 436

Year of Publication: 1998

ISBN:1-58113-008-2

Authors

Yanbing Li	Department of Electrical Engineering, Princeton University, Princeton, NJ
Wayne Wolf	Department of Electrical Engineering, Princeton University, Princeton, NJ

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 14, Citation Count: 8

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Koen Danckaert , Francky Catthoor , Hugo de Man, System level memory optimization for hardware-software co-design, Proceedings of the 5th International Workshop on Hardware/Software Co-Design, p.55, March 24-26, 1997
	2	Bharat P. Dave , Ganesh Lakshminarayana , Niraj K. Jha, COSYN: hardware-software co-synthesis of embedded systems, Proceedings of the 34th annual conference on Design automation, p.703-708, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266341]
	3	Rolf Ernst , Jorg Henkel , Thomas Benner, Hardware-Software Cosynthesis for Microcontrollers, IEEE Design & Test, v.10 n.4, p.64-75, October 1993 [doi>10.1109/54.245964]
	4	Rajesh K. Gupta , Giovanni De Micheli, Hardware-Software Cosynthesis for Digital Systems, IEEE Design & Test, v.10 n.3, p.29-41, July 1993 [doi>10.1109/54.232470]
	5	Junwei Hou , Wayne Wolf, Process Partitioning for Distributed Embedded Systems, Proceedings of the 4th International Workshop on Hardware/Software Co-Design, p.70, March 18-20, 1996
	6	D. Kirk and J. Strosnider, "SMART(strategic memory allocation for real-time) cache design using the MIPS R3000;' in Proceedings, 1 lth Real-time Systems Symposium, 1990.
	7	Chang-Gun Lee , J. Hahn , Sang Lyul Min , R. Ha , Seongsoo Hong , Chang Yun Park , Minsuk Lee , Chong Sang Kim, Analysis of cache-related preemption delay in fixed-priority preemptive scheduling, Proceedings of the 17th IEEE Real-Time Systems Symposium (RTSS '96), p.264, December 04-06, 1996
	8	Yanbing Li , Wayne Wolf, A task-level hierarchical memory model for system synthesis of multiprocessors, Proceedings of the 34th annual conference on Design automation, p.153-156, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266053]
	9	Yanbing Li , Wayne Wolf, Hierarchical Scheduling and Allocation of Multirate Systems on Heterogeneous Multiprocessors, Proceedings of the 1997 European conference on Design and Test, p.134, March 17-20, 1997
	10	Yau-Tsun Steven Li , Sharad Malik , Andrew Wolfe, Performance estimation of embedded software with instruction cache modeling, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.380-387, November 05-09, 1995, San Jose, California, United States
	11	C. L. Liu , James W. Layland, Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment, Journal of the ACM (JACM), v.20 n.1, p.46-61, Jan. 1973 [doi>10.1145/321738.321743]
	12	S. Prakash and A. Parker, "SOS: synthesis of application-specific heterogeneous multiprocessor systems;' Journal of Parallel and Distributed Computing, vol.l 6, pp.338-351,1992.
	13	K. Ramamritham, "Allocation and scheduling of complex periodic tasks" In Proceedings, International Conference on Distributed Computing Systems, 1990.
	14	Frank Vahid , Daniel D. Gajski , Jie Gong, A binary-constraint search algorithm for minimizing hardware during hardware/software partitioning, Proceedings of the conference on European design automation, p.214-219, September 19-23, 1994, Grenoble, France
	15	Wayne H. Wolf, An architectural co-synthesis algorithm for distributed, embedded computing systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.5 n.2, p.218-229, June 1997 [doi>10.1109/92.585225]
	16	W. Wolf. "Hardware-software co-design of embedded systems" Proceedings of the IEEE, July 1994.
	17	Ti-Yen Yen , Wayne Wolf, Communication synthesis for distributed embedded systems, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.288-294, November 05-09, 1995, San Jose, California, United States
	18	Motion Pictures Experts Group ISO-IEC/JTCl/SC29AVG11. "Information technology-Coding of moving pictures and associated audio for digital media at up to about 1.5 Mbit/s;' 1992.
	19	W. Ye et al., "Fast Timing Analysis for Hardware-So,rare Co- Synthesis;', ICCD93, 1993.
	20	John L. Hennessy , David A. Patterson, Computer architecture (2nd ed.): a quantitative approach, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1996

CITED BY 8

	Neal K. Tibrewala , JoAnn M. Paul , Donald E. Thomas, Modeling and evaluation of hardware/software designs, Proceedings of the ninth international symposium on Hardware/software codesign, p.11-16, April 2001, Copenhagen, Denmark
	JoAnn M. Paul , Arne J. Suppé , Donald E. Thomas, Modeling and simulation of steady state and transient behaviors for emergent SoCs, Proceedings of the 14th international symposium on Systems synthesis, September 30-October 03, 2001, Montréal, P.Q., Canada
	P. R. Panda , F. Catthoor , N. D. Dutt , K. Danckaert , E. Brockmeyer , C. Kulkarni , A. Vandercappelle , P. G. Kjeldsberg, Data and memory optimization techniques for embedded systems, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.6 n.2, p.149-206, April 2001
	Yanbing Li , Wayne H. Wolf, Hardware/software co-synthesis with memory hierarchies, Readings in hardware/software co-design, Kluwer Academic Publishers, Norwell, MA, 2001
	Zhao Wu , Wayne Wolf, Iterative cache simulation of embedded CPUs with trace stripping, Proceedings of the seventh international workshop on Hardware/software codesign, p.95-99, March 1999, Rome, Italy
	JoAnn M. Paul , Simon N. Peffers , Donald E. Thomas, A codesign virtual machine for hierarchical, balanced hardware/software system modeling, Proceedings of the 37th conference on Design automation, p.390-395, June 05-09, 2000, Los Angeles, California, United States
	Hemendra Singh Negi , Tulika Mitra , Abhik Roychoudhury, Accurate estimation of cache-related preemption delay, Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, October 01-03, 2003, Newport Beach, CA, USA
	Alessandro Pinto , Alvise Bonivento , Allberto L. Sangiovanni-Vincentelli , Roberto Passerone , Marco Sgroi, System level design paradigms: Platform-based design and communication synthesis, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.11 n.3, p.537-563, July 2006