Integrating floorplanning in data-transfer based high-level synthesis

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Integrating floorplanning in data-transfer based high-level synthesis

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International Conference on Computer Aided Design archive
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California, United States

Pages: 412 - 417

Year of Publication: 1998

ISBN:1-58113-008-2

Authors

Shantanu Tarafdar	Synopsys Inc., 700 East Middlefield Rd., Mountain View, CA
Miriam Leeser	Dept. of Electrical and Computer Engineering, Northeastern University, Boston, MA
Zixin Yin	Dept. of Electrical and Computer Engineering, Northeastern University, Boston, MA

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 5, Citation Count: 6

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Shantanu Tarafdar , Miriam Leeser, The DT-model: high-level synthesis using data transfers, Proceedings of the 35th annual conference on Design automation, p.114-121, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277069]
	2	S. Tarafdar, A Data-Transfer Model For High Level Synthesis And Its Application In Storage And Interconnect Optimization. PhD thesis, Cornell University, 1998.
	3	F. Kurdahi, D. D. Gajski, C. Ramachandran, and V. Chaiyakul, "Linking Register-Transfer and Physical Levels of Design," 1EICE Transactions on Information and Systems, September 1993.
	4	M. C. MeFarland and T. j. Kowalski, "Incorporating bottomup design into hardware synthesis," IEEE Transactions on Computer-Aided Design, vol. 9, pp. 938-950, September 1990.
	5	D. W. Knapp, "Fasolt: A Program for Feedback-Driven Data- Path Optimization," IEEE Transactions on Computer-A~ded Design, vol. 11, pp. 677-695, June 1992.
	6	Jen-Pin Weng , Alice C. Parker, 3D scheduling: high-level synthesis with floorplanning, Proceedings of the 28th conference on ACM/IEEE design automation, p.668-673, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127748]
	7	M. Rim, A. Majumdar, R. Jain, and R. De Leone, "Optimal and Heuristic Algorithms for Solving the Binding Problem," IEEE Transactions on VLSI Systems, vol. 2, pp. 211-225, June 1994.
	8	M. MeFarland, "A Fast Floor Planning Algorithm for Architectural Evaluation," Proceedings of the International Conference on Computer Design, pp. 96-99, October 1989.
	9	W. Kernighan and S. Lin, "An Efficient Heuristie Procedure for Partitioning Graphs," Bell Systems Technical Journal, vol. 49, pp. 291-307, 1970.

CITED BY 6

	Jinhwan Jeon , Daehong Kim , Dongwan Shin , Kiyoung Choi, High-level synthesis under multi-cycle interconnect delay, Proceedings of the 2001 conference on Asia South Pacific design automation, p.662, January 2001, Yokohama, Japan
	William E. Dougherty , Donald E. Thomas, Unifying behavioral synthesis and physical design, Proceedings of the 37th conference on Design automation, p.756-761, June 05-09, 2000, Los Angeles, California, United States
	Daehong Kim , Jinyong Jung , Sunghyun Lee , Jinhwan Jeon , Kiyoung Choi, Behavior-to-placed RTL synthesis with performance-driven placement, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Junhyung Um , Jae-hoon Kim , Taewhan Kim, Layout-driven resource sharing in high-level synthesis, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.614-618, November 10-14, 2002, San Jose, California
	Junhyung Um , Taewhan Kim, Resource Sharing Combined with Layout Effects in High-Level Synthesis, Journal of VLSI Signal Processing Systems, v.44 n.3, p.231-243, September 2006
	Kyoung-Hwan Lim , YongHwan Kim , Taewhan Kim, Interconnect and communication synthesis for distributed register-file microarchitecture, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California