Architecture driven circuit partitioning

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Architecture driven circuit partitioning

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International Conference on Computer Aided Design archive
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California, United States

Pages: 408 - 411

Year of Publication: 1998

ISBN:1-58113-008-2

Authors

Chau-Shen Chen	Department of Computer Science, National Tsing Hua University, HsinChu, Taiwan 30043
TingTing Hwang	Department of Computer Science, National Tsing Hua University, HsinChu, Taiwan 30043
C. L. Liu	Department of Computer Science, National Tsing Hua University, HsinChu, Taiwan 30043

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Michael Butts , Jon Batcheller , Joseph Varghese, An Efficient Logic Emulation System, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.138-141, October 11-14, 1992
	2	James Hwang , Abbas El Gamal, Optimal replication for min-cut partitioning, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.432-435, November 1992, Santa Clara, California, United States
	3	Nan-Chi Chou, Lung-Tien Liu, Chung-Kuan Cheng and Wei-Jin Dai, "Local Ratio Cut and Set Covering Partitioning for Huge Logic Emulation Systems," IEEE Transaction on CAD, Vol. 14, No. 9, September 1995, pp. 1085-1092.
	4	"A General Purpose Multiple-Way Partitioning Algorithm," IEEE Transactions on CAD, Vol. 13, no. 12, December~ 1994, pp.1480-1488.
	5	Wai-Kei Mak , D. F. Wong, On optimal board-level routing for FPGA-based logic emulation, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.552-556, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217586]
	6	Shiuann-Shiuh Lin, Yuh-Ju Lin and TingTing H- wang, "Net Assignment for FPGA-based Logic Emulation System in Folded-Clos Network Structure," IEEE Transactions on CAD, Vol. 16, no. 3, March, 1997, pp.316-320.