On the optimization power of retiming and resynthesis transformations

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On the optimization power of retiming and resynthesis transformations

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International Conference on Computer Aided Design archive
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California, United States

Pages: 402 - 407

Year of Publication: 1998

ISBN:1-58113-008-2

Authors

Rajeev K. Ranjan	Synopsys Inc., Mountain View, CA
Vigyan Singhal	Cadence Berkeley Labs, Berkeley, CA
Fabio Somenzi	University of Colorado, Boulder, Boulder, CO
Robert K. Brayton	University of California, Berkeley, Berkeley, CA

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 5, Citation Count: 4

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	R. K. Brayton, R. Rudcll, A. L. Sangiovanni-Vincentclli, and A. R. Wang. MIS: A Multiple-Level Logic Optimization System. IEEE Trans. Comput.-Aided Design Integrated Circuits, CAD-6(6): 1062-8 I, Nov. 1987.
	2	S. Hassoun and C. Ebling. Sequential Circuit Optimization Using Precomputation. In Proc. IEEE/ACM intl. gbrkshop on Logic S3v~thesis, May 1997.
	3	Balakrishnan Iyer , Maciej Ciesielski, Metamorphosis: state assignment by retiming and re-encoding, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.614-617, November 10-14, 1996, San Jose, California, United States
	4	C. Legl, R Vanbckbcrgen, and A. Wang. Refiming of Edge-Triggered Circuits with Mulitple Clocks and Load Enables. In Proc. IEEE/ACM Intl. Workshop on Logic S~thesis, 1997.
	5	C.E. Leiserson and J. B. Saxe. Optimizing Synchronous Systems. Journal of VLSI and Computer Systems, I(I):41-67, Spring 1983.
	6	Sharad Malik, Combinational logic optimization techniques in sequential logic synthesis, University of California at Berkeley, Berkeley, CA, 1991
	7	Vigyan Singhal , Carl Pixley , Richard L. Rudell , Robert K. Brayton, The validity of retiming sequential circuits, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.316-321, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217548]
	8	H. Zhou, V. Singhal, and A. Aziz. How Powerful is Retiming? In Proc. IEEE/ACM Intl. gbrkshop on Logic S3~thesis, May 1998.

CITED BY 4

	Enrique San Millán , Luis Entrena , José Alberto Espejo, On the optimization power of redundancy addition and removal techniques for sequential circuits, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Enrique San Millán , Luis Entrena , José Alberto Espejo , Celia López, Theoretical comparison between sequential redundancy addition and removal and retiming optimization techniques, Journal of Systems Architecture: the EUROMICRO Journal, v.49 n.12-15, p.529-541, December 2003
	Girish Venkataramani , Seth C. Goldstein, Operation chaining asynchronous pipelined circuits, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
	Chris Chu , Evangeline F. Y. Young , Dennis K. Y. Tong , Sampath Dechu, Retiming with Interconnect and Gate Delay, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.221, November 09-13, 2003