Asymptotically efficient retiming under setup and hold constraints

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Asymptotically efficient retiming under setup and hold constraints

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International Conference on Computer Aided Design archive
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California, United States

Pages: 396 - 401

Year of Publication: 1998

ISBN:1-58113-008-2

Author

Marios C. Papaefthymiou

Advanced Computer Architecture Laboratory, Department of Electrical Engineering and Computer Science, Univesity of Michigan Ann Arbor, MI

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 12, Citation Count: 9

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Thomas T. Cormen , Charles E. Leiserson , Ronald L. Rivest, Introduction to algorithms, MIT Press, Cambridge, MA, 1990
	2	S. Dey and S. Chakradhar. Retiming sequential circuits to enh-xnce testability. In Proceedings of the I2th IEEE VLSI T~st Symposium, pages 28-33, April 1994.
	3	Alexander T. Ishii, Retiming gated-clocks and precharged circuit structures, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.300-307, November 07-11, 1993, Santa Clara, California, United States
	4	Alexander T. Ishii , Charles E. Leiserson , Marios C. Papaefthymiou, Optimizing two-phase, level-clocked circuitry, Journal of the ACM (JACM), v.44 n.1, p.148-199, Jan. 1997 [doi>10.1145/256292.256301]
	5	A. T. Ishii and M. C. Papaefthymiou. Efficient pipelining of level-clocked circuits with rain-max propagation delays. In TAU'95 A CM international Workshop or~ Timing Issues in the Specification and Synthesis o.f Digital Systems, November 1995.
	6	K.N. Lalgudi and M. C. Papaefthymiou. Retiming edgetriggered circuits under general delay models. IEEE Transactions on Computer-Aided Design o.f Integrated Circuits, 16(12):1393-1408, December 1997.
	7	(2. E. Leiserson and J. B. Saxe. Optimizing synchronous systems. Journal of VLSI and Computer Systems, 1 (1):41-67, 1983.
	8	C. E. Leiserson and J. B. Saxe. Retiming synchronous circuitry. Algorithmica, 6(1), 1991. Also available as MIT/LCS/TM-372.
	9	B. Lockyear and C. Ebeling. Optimal retiming of multi-phase, level-clocked circuits. In A d~,anced Research in VLSI and Parallel Systems: Proc. o.f the I992 Brown/MIT Conference. MIT Press, March 1992.
	10	Brian Lockyear , Carl Ebeling, The practical application of retiming to the design of high-performance systems, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.288-295, November 07-11, 1993, Santa Clara, California, United States
	11	S. Malik, E. Sentovich, R. K. Brayton, and A. Sangiovanni-Vincentelli. Retiming and resynthesis: Optimizing sequential networks with combinational techniques. In Proc. o.f the Hawaii International Conference on System Sciences, June 1990.
	12	Marios C. Papaefthymiou, Understanding retiming through maximum average-delay cycles, Mathematical Systems Theory, v.27 n.1, p.65-84, Jan./Feb. 1994
	13	Marios C. Papaefthymiou , Keith H. Randall, TIM: a timing package for two-phase, level-clocked circuitry, Proceedings of the 30th international conference on Design automation, p.497-502, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164998]
	14	K. A. Sakallah, T. N. Mudge, T. M. Burks, and E. S. Davidson. Synchronization of pipelines. IEEE Transactions on Computer-Aided Design o.f Integrated Circuits and Systems, 12(8):1132-1146, August 1993.
	15	Narendra V. Shenoy , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli, Retiming of Circuits with Single Phase Transparent Latches, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.86-89, October 14-16, 1991
	16	Narendra V. Shenoy , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli, Minimum padding to satisfy short path constraints, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.156-161, November 07-11, 1993, Santa Clara, California, United States
	17	T. Soyata, E. Friedman, and J. Mulligan. Incorporating interconnect, register, and clock distribution delays into the retiming process. IEEE Transactions on Computer-Aided Design o.f Integrated Circuits and Systems, 16(1):105-120, January 1997.

CITED BY 9

	Soha Hassoun , Tiziano Villa, Optimization of synchronous circuits, Logic Synthesis and Verification, Kluwer Academic Publishers, Norwell, MA, 2001
	Vijay Sundararajan , Sachin S. Sapatnekar , Keshab K. Parhi, MINFLOTRANSIT: min-cost flow based transistor sizing tool, Proceedings of the 37th conference on Design automation, p.649-664, June 05-09, 2000, Los Angeles, California, United States
	Vijay Sundararajan , Sachin S. Sapatnekar , Keshab K. Parhi, Marsh: min-area retiming with setup and hold constraints, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.2-6, November 07-11, 1999, San Jose, California, United States
	Ingmar Neumann , Wolfgang Kunz, Placement driven retiming with a coupled edge timing model, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Vijay Sundararajan , Sachin S. Sapatnekar , Keshab K. Parhi, A new approach for integration of min-area retiming and min-delay padding for simultaneously addressing short-path and long-path constraints, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.9 n.3, p.273-289, July 2004
	Chuan Lin , Hai Zhou, An efficient retiming algorithm under setup and hold constraints, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Chris Chu , Evangeline F. Y. Young , Dennis K. Y. Tong , Sampath Dechu, Retiming with Interconnect and Gate Delay, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.221, November 09-13, 2003
	Ulrich Seidl , Klaus Eckl , Frank Johannes, Performance-Directed Retiming for FPGAs Using Post-Placement Delay Information, Proceedings of the conference on Design, Automation and Test in Europe, p.10770, March 03-07, 2003
	Shih-Hsu Huang , Yow-Tyng Nieh, Clock skew scheduling with race conditions considered, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.12 n.4, p.45-es, September 2007