Using precomputation in architecture and logic resynthesis

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Using precomputation in architecture and logic resynthesis

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International Conference on Computer Aided Design archive
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California, United States

Pages: 316 - 323

Year of Publication: 1998

ISBN:1-58113-008-2

Authors

Soha Hassoun	Tufts University, Medford, MA
Carl Ebeling	University of Washington, Seattle, WA

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 10, Citation Count: 4

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	S. Bommu. "Sequential Logic Optimization with Implicit Retiming". Master's thesis, University of Massachusetts, 1996.
	2	G. De Micheli. "Synchronous Logic Synthesis: Algorithms for Cycle-Time Minimization". IEEE Transactions on Computer- Aided Design, 10(1):63-73, Jan. 1991.
	3	Sujit Dey , Franc Brglez , Gershon Kedem, Partitioning Sequential Circuits for Logic Optimization, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.70-76, October 14-16, 1991
	4	John P. Fishburn, A depth-decreasing heuristic for combinational logic: or how to convert a ripple-carry adder into a carry-lookahead adder or anything in-between, Proceedings of the 27th ACM/IEEE conference on Design automation, p.361-364, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123305]
	5	Soha Hassoun , Carl Ebeling, Architectural retiming: pipelining latency-constrained circuits, Proceedings of the 33rd annual conference on Design automation, p.708-713, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240652]
	6	Peter M. Kogge, The Architecture of Symbolic Computers, McGraw-Hill, Inc., New York, NY, 1990
	7	C. Leiserson, r. Rose, and J. Sa~xe. "Optimizing Synchronous Circuitry by Retiming". In Proc. of the 3rd Caltech Conference on VLSI, pages 87-116, Mar. 1983.
	8	S. Malik, E. Sentovich, R. Brayton, and A. Sangiovanni- Vincentelli. "Retiming and Resynthesis: Optimizing Sequential Networks with Combinational Techniques". IEEE Transactions on Computer-Aided Design, 10(1):74-84, Jan. 1991.
	9	K. Parhi. "Look-ahead in Dynamic Programming and Quantizer Loops". In IEEE International Symposium on Circuits and Systems, pages 1382-7, 1989.
	10	David A. Patterson , John L. Hennessy, Computer architecture: a quantitative approach, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1990
	11	E. Sentovich, K. Singh, L. Lavagno, C. Moon, lt. Murgai, A. Saldanha, H. Savoj, P. Stephan, R. Brayton, and A. Sangiox-anni- Vincentelli. "SIS: A System for Sequential Circuit Synthesis". Technical Report UCB/ERL M92/41, University of California, Dept. of Electmcal Engineering and Computer Science, May 1992.

CITED BY 4

	Soha Hassoun , Tiziano Villa, Optimization of synchronous circuits, Logic Synthesis and Verification, Kluwer Academic Publishers, Norwell, MA, 2001
	Soha Hassoun, Fine grain incremental rescheduling via architectural retiming, Proceedings of the 11th international symposium on System synthesis, p.158-163, December 02-04, 1998, Hsinchu, Taiwan, China
	Shi-Yu Huang, On speeding up extended finite state machines using catalyst circuitry, Proceedings of the 2001 conference on Asia South Pacific design automation, p.583-588, January 2001, Yokohama, Japan
	Timothy Kam , Michael Kishinevsky , Jordi Cortadella , Marc Galceran-Oms, Correct-by-construction microarchitectural pipelining, Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, November 10-13, 2008, San Jose, California