Technology mapping for domino logic

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Technology mapping for domino logic

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International Conference on Computer Aided Design archive
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California, United States

Pages: 248 - 251

Year of Publication: 1998

ISBN:1-58113-008-2

Authors

Min Zhao	Department of Electrical and Computer Engineering, University of Minnesota, 200 Union Street SE, Minneapolis MN
Sachin S. Sapatnekar	Department of Electrical and Computer Engineering, University of Minnesota, 200 Union Street SE, Minneapolis MN

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 14, Citation Count: 13

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	K. Keutzer, DAGON: technology binding and local optimization by DAG matching, Proceedings of the 24th ACM/IEEE conference on Design automation, p.341-347, June 28-July 01, 1987, Miami Beach, Florida, United States [doi>10.1145/37888.37940]
	2	E. Detjens, G. Gannot, R. Rudell, A. Sangiovanni- Vincentelli, and A. Wang, "Technology mapping in MIS," in Proc. IEEE/ACM Int. Conf. Computer- Aided Design, pp. 116-119, 1987.
	3	K. Chaudhary and M. Pedram, "Computing the area versus delay trade-off curves in technology mapping," IEEE Transactions on Comput.-Aided Design, vol. 14, pp. 1480-1489, Dec. 1995.
	4	M. R. C. M. Berkelaar and J. A. G. Jess, "Technology mapping for standard-cell generators," in Proc. IEEE/A CM Int. Conf. Computer-Aided Design, pp. 470-473, 1988.
	5	M. R. Prasad, D. Kirkpatrick, and R. K. Brayton, "Domino logic synthesis and technology mapping," in Int. Workshop on Logic Synthesis, 1997.
	6	Ruchir Puri , Andrew Bjorksten , Thomas E. Rosser, Logic optimization by output phase assignment in dynamic logic synthesis, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.2-7, November 10-14, 1996, San Jose, California, United States
	7	Thomas T. Cormen , Charles E. Leiserson , Ronald L. Rivest, Introduction to algorithms, MIT Press, Cambridge, MA, 1990
	8	T. Williams, "Dynamic Logic: Clocked and Asynchronous," Tutorial notes at the Int. Solid State Circuits Conf., 1996.
	9	J. Wang, Z. D. Wang, G. A. Jullien, and W. C. Miller, "Area-time analysis of carry lookahead adders using enhanced multiple output domino logic," in Proc. IEEE Int. Syrup. Circuits Syst., pp. 59-62, 1994.
	10	Z. Wang, G. A. Jullien, W. C. Miller, J. Wang, and S. S. Bizzan, "Fast adders using enhanced multipleoutput domino logic," IEEE J. Solid-State Circuits, vol. 32, pp. 206-213, Feb. 1997.

CITED BY 13

	Ki-Wook Kim , Unni Narayanan , Sung-Mo Kang, Domino logic synthesis minimizing crosstalk, Proceedings of the 37th conference on Design automation, p.280-285, June 05-09, 2000, Los Angeles, California, United States
	Min Zhao , Sachin S. Sapatnekar, Technology mapping algorithms for domino logic, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.7 n.2, p.306-335, April 2002
	Srirang K. Karandikar , S. Sapatnekar, Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect, Proceedings of the 38th conference on Design automation, p.377-382, June 2001, Las Vegas, Nevada, United States
	Tyler J. Thorp , Gin S. Yee , Carl M. Sechen, Design and synthesis of dynamic circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.1, p.141-149, February 2003
	Ki-Wook Kim , Seong-Ook Jung , Unni Narayanan , C. L. Liu , Sung-Mo Kang, Noise-aware interconnect power optimization in domino logic synthesis, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.1, p.79-89, February 2003
	Min Zhao , Sachin S. Sapatnekar, Timing-driven partitioning for two-phase domino and mixed static/domino implementations, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.107-110, November 07-11, 1999, San Jose, California, United States
	Ki-Wook Kim , Seong-Ook Jung , Unni Narayanan , C. L. Liu , Sung-Mo Kang, Noise-aware power optimization for on-chip interconnect, Proceedings of the 2000 international symposium on Low power electronics and design, p.108-113, July 25-27, 2000, Rapallo, Italy
	Naran Sirisantana , Aiqun Cao , Shawn Davidson , Cheng Kok Koh , Kaushik Roy, Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications, Proceedings of the 2001 international symposium on Low power electronics and design, p.267-270, August 2001, Huntington Beach, California, United States
	Aiqun Cao , Naran Sirisantana , Cheng-Kok Koh , Kaushik Roy, Synthesis of skewed logic circuits, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.10 n.2, p.205-228, April 2005
	Aiqun Cao , Ruibing Lu , Cheng-Kok Koh, Post-layout logic duplication for synthesis of domino circuits with complex gates, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Aiqun Cao , Ruibing Lu , Chen Li , Cheng-Kok Koh, Postlayout optimization for synthesis of Domino circuits, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.11 n.4, p.797-821, October 2006
	Yi-Yu Liu , Ting Ting Hwang, Crosstalk-aware domino logic synthesis, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Debasis Samanta , Ajit Pal , Nishant Sinha, Synthesis of High Performance Low Power Dynamic CMOS Circuits, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.99, January 07-11, 2002