Domino logic synthesis using complex static gates

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Domino logic synthesis using complex static gates

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International Conference on Computer Aided Design archive
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California, United States

Pages: 242 - 247

Year of Publication: 1998

ISBN:1-58113-008-2

Authors

Tyler Thorp	Department of Eledrid Engineering, University of Washington, Seattle, WA
Gin Yee	Department of Eledrid Engineering, University of Washington, Seattle, WA
Carl Sechen	Department of Eledrid Engineering, University of Washington, Seattle, WA

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 7, Downloads (12 Months): 35, Citation Count: 8

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	B. Be~ider, A. Bhck, et al., "A 300-MHz 64-b quad-issue CMOS RISC microprocessor," IEEE J. Solid-State Circuits, voL 30, no. 11, pp. 1203-1214, Nov. 1995.
	2	R. Brayton, C.L. Chert, Y. J. Yamour, '%~_~thod for optimizing logic for single-ended domino logic circuits," IBM Technical Disclosure Bulletin, vol. 27, no. 7}3, pp. 4398-4401, Dec. 1984.
	3	R. Brayton, C.L. Chen, C. McMuUen, R. Otten, and Y. J. Yamour, "Automated implementation of switching functions as dynamic CMOS circuits," Proc. IEEE Custom Integrated Circuits Conference, May 1984, pp. 346-350.
	4	A. Chamas, et. al., "A 64b microprocessor with multimedia support," ISSCC Dig. of Tech. Papers, Feb 1995, pp. 177-179.
	5	R. ColweU and tL Steck, "A 0.6ram BiCMOS processor with dyn,m~c execufi~a," ISSCC Dig. of Tech. Papers, Feb. 1995, pp. 176-177.
	6	G. De Micheli, '~Perfcrmance-oriented synthesis of large-scale domino CMOS ckcuits," IEEE Trans. Computer-Aided Design, vol. CAD-6, no. 5, pp. 751-765, Sep. 1987.
	7	E. Detjeas, G. Gannot, R. Rudell, A. SangiovArmi-V'mcentelli, and A. Wang, 'Technology mapping in MIS," IEEEIACM Int. Conf. on Computer-Aided Design, pp 116-119, 1987.
	8	Tom Fletcher, private comm-nication, Imel Corporalion, May 1997.
	9	V. Friedman and S. Liu, 'Tlynamlc logic CMOS circuits," IEEE 3". Solid-State Circuits, vol. SC-19, no. 2, pp. 263-266, Apr. 1984.
	10	N. Goncalves and H. De Man, "NORA: a rac.zfree dyn,mlc CMOS technique for pipelined logic structures," IEEE Z Solid-State Circuits, vol. SC-18, no. 3, pp. 614-619, June 1983.
	11	JR. Gu and M. ~masry, "AU-N-logie high-~ truesingle-phase dynamic CMOS logic," IEEE J. Solid- State Circuits, vol. 31,11o. 2, pp. 221-9, Feb. 1996.
	12	L. Heller and W. Griffin, "Cascade voltage switch logic: a differential CMOS logic family," ISSCC Dig. of Tech. Papers, pp. 16-17, 1984.
	13	M. Hofinana and A. Newton, "A domino CMOS logic synthesis system," Proc. IEEE Int. Symposium on Curcults and Systems, pp. 411-414, 1985.
	14	Y. ji-ren and C. Svensson, "High-speed CMOS circuit technique," IEEE J. Solid-State Circuits, vol. 24, no. 1, pp. 62-70, Feb 1989.
	15	R. tL Krambeck, C. M. Lee, H. S. Law, '~/igh-speed compact circuits with CMOS," IEEE J. Solid-State Circuits, vol. SC-17, no. 3, pp. 614-619, June 1982.
	16	Patrik Larsson and Christer Sveasson, "No'me in digital dynamic CMOS circuits," IEEE f. Solid-State Circuits, vol. SC-29, no. 3, pp. 655-662, June 1994.
	17	C. Lee andE. Szeto, "Zipper CMOS," IEEE Circuits and Devices Magazine, pp. 10-16, May 1986.
	18	V. (3. Oklobdzija and R. K. Montoye, 'T)e, siga-performance tradeoffs in CMOS domino logic," Proc. IEEE 1985 Custom integrated Circuits Conf., pp. 334-337, May 1985.
	19	M. R. Prasad, D. Kirkpatrick, ILK. Braytoa, and A. L. Sangiovanni-V'mcenteUi, "Domino logic synthesis and technology mapping," Proc. Int. Workshop on Logic Synthesis, May 1997, vol. 1.
	20	J. A. Pretorius, A. S. Shubat, and C. A. T Sahma, "Charge redistribution and noise margins in Domino CMOS logic," IEEE Transactions on Circuits and System& vol CAS-33, no. 8, pp. 786-793, August 1986.
	21	Ruchir Puri , Andrew Bjorksten , Thomas E. Rosser, Logic optimization by output phase assignment in dynamic logic synthesis, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.2-7, November 10-14, 1996, San Jose, California, United States
	22	E. Sentovich, K. Singh, L. Lavagno, C. Moon, tL Murgai, A. Saldanha, H. Savoj, P. Stephan, R. Brayton, and A. Sangiovanni-VincenteUi, "SIS: a system for sequential circuit synthesis," Technical Report UCB/ERL M92/41, University of California, Berkeley, CA, May 1992.
	23	G. Ye~ and C Sechen, '7)ynamic Logic Synthesis," Proc. IEEE Custom integrated Circuits Conference, May 1997, pp. 345-348.

CITED BY 8

	Jovanka Ciric , Gin Yee , Carl Sechen, Delay minimization and technology mapping of two-level structures and implementation using clock-delayed domino logic, Proceedings of the conference on Design, automation and test in Europe, p.277-282, March 27-30, 2000, Paris, France
	Min Zhao , Sachin S. Sapatnekar, Technology mapping algorithms for domino logic, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.7 n.2, p.306-335, April 2002
	Tyler J. Thorp , Gin S. Yee , Carl M. Sechen, Design and synthesis of dynamic circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.1, p.141-149, February 2003
	Tyler Thorp , Gin Yee , Carl Sechen, Monotonic static CMOS and dual-VT technology, Proceedings of the 1999 international symposium on Low power electronics and design, p.151-155, August 16-17, 1999, San Diego, California, United States
	Min Zhao , Sachin S. Sapatnekar, Timing-driven partitioning for two-phase domino and mixed static/domino implementations, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.107-110, November 07-11, 1999, San Jose, California, United States
	Miguel E. Litvin , Samiha Mourad, Self-reset logic for fast arithmetic applications, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.13 n.4, p.462-475, April 2005
	W. Belluomini , D. Jamsek , A. K. Martin , C. McDowell , R. K. Montoye , H. C. Ngo , J. Sawada, Limited switch dynamic logic circuits for high-speed low-power circuit design, IBM Journal of Research and Development, v.50 n.2/3, p.277-286, March 2006
	Debasis Samanta , Ajit Pal , Nishant Sinha, Synthesis of High Performance Low Power Dynamic CMOS Circuits, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.99, January 07-11, 2002