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Determination of worst-case aggressor alignment for delay calculation
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Source International Conference on Computer Aided Design archive
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design table of contents
San Jose, California, United States
Pages: 212 - 219  
Year of Publication: 1998
ISBN:1-58113-008-2
Authors
Paul D. Gross  Department of Electrical and Computer Engineetig, Carnegie Mellon University, Pittsburgh, PA
Ravishankar Arunachalam  Department of Electrical and Computer Engineetig, Carnegie Mellon University, Pittsburgh, PA
Karthik Rajagopal  Department of Electrical and Computer Engineetig, Carnegie Mellon University, Pittsburgh, PA
Lawrence T. Pileggi  Department of Electrical and Computer Engineetig, Carnegie Mellon University, Pittsburgh, PA
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 3,   Downloads (12 Months): 32,   Citation Count: 42
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
Semiconductor Industry Association (SIA), "The National Technology Roadmap for Semiconductors," 1994.
2
 
3
G. Yee, R. Chandra, V. Ganesan and C. Sechen, "Wire Delay in the Presence of Crosstalk," Proceedings of TAU 97, the IEEE meeting on Timing Issues in Digital Systems, December 1997.
 
4
 
5
L.T. Pillage and R.A. Rohrer, "Asymptotic Wavefonn Evaluation for Tuning Analysis," IEEE Trans. Computer-Aided Design, April 1990.
 
6
 
7
Peter Feldmann and Roland W. Frcund, "Efficient Linear Circuit Analysis by Pade Approximation via the Lanczos Process," IEEE Trans. Computer-Aided Design, May 1995.
 
8
9
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11
E.Lelarasmee, A.E.Ruetfli and A.L. Sangiovanni-Vincentelli, "The Waveform Relaxation Method for Time-domain Analysis of Large Scale Integrated Circuits and Systems," IEEE Trans. Computer- Aided Design, July 1982.
 
12
LL Arunachalam, F. Dartu and L.T. Pileggi, "CMOS Gate Delay Models for General RLC Loading," Proceedings of the International Conference of Computer-Aided Design, November 1997.
 
13
M.E. Van Valkenburg, "introduction to Modern Network Synthesis," John Wiley & Sons, Inc., 1960.
 
14
Florentin Dartu, "Gate- and Transistor-Level Waveform Calculation for Timing Analysis," Ph.D. Dissertation, Carnegie Mellon University, August 1997.
15
 
16
G.D. Gristede, A.E. Ruehli and C.A. Zukowski, "Convergence Properties of Waveform Relaxation Circuit Simulation Methods," Technical Report, IBM T.L Watson Research Center, 1996.
 
17
U. Miekkala, O. Nevanlinna and A.E. Ruehli, "Convergence and Circuit Partitioning Aspects for Waveform Relaxation," Technical Report, IBM T.J. Watson Research Center, 1990.
 
18
Ravishankar Arunachalam, "CMOS Gate-Delay Models for Coupled RC(L) Interconnect Loads," M.S. Thesis, Carnegie Mellon University, May 1998.

CITED BY  42

Collaborative Colleagues:
Paul D. Gross: colleagues
Ravishankar Arunachalam: colleagues
Karthik Rajagopal: colleagues
Lawrence T. Pileggi: colleagues