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Test set compaction algorithms for combinational circuits
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Source International Conference on Computer Aided Design archive
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design table of contents
San Jose, California, United States
Pages: 283 - 289  
Year of Publication: 1998
ISBN:1-58113-008-2
Authors
Ilker Hamzaoglu  Center for Reliable & High-Performance Computing, University of Illinois, Urbana, IL
Janak H. Patel  Center for Reliable & High-Performance Computing, University of Illinois, Urbana, IL
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 9,   Downloads (12 Months): 40,   Citation Count: 53
Additional Information:

references   cited by   index terms   collaborative colleagues  

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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6
P. Goel and B.C. Rosales, "Test Generation and DynamieCompaction of Tests", in Digest of Papers 1979 Test Conf., pp. 189-192, October 1979.
 
7
I. Hamzaoglu , J. H. Patel, 20.2 New Techniques for Deterministic Test Pattern Generation, Proceedings of the 16th IEEE VLSI Test Symposium, p.446, April 26-30, 1998
8
Seiji Kajihara , Irith Pomeranz , Kozo Kinoshita , Sudhakar M. Reddy, Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits, Proceedings of the 30th international conference on Design automation, p.102-106, June 14-18, 1993, Dallas, Texas, United States  [doi>10.1145/157485.164617]
 
9
S. Kajihara, I. Pomeranz, K. Kinoshita and S. M. Reddy, "Cost Effective Generation of Minimal Test Sets for Stuck at Faults in Combinational Logic Circuits", IEEE Trans. on Computer-Aided Design, pp. 1496-1504,December 1995.
 
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B. Krishnamurthy and S. B. Akers, "On the Complexity of Estimating the Size of a Test Set", IEEE Trans. on Computers, pp. 750-753, August 1984.
 
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Y. Matsunaga, "MINT- An Exact Algorithm for Finding Minimum Test Sets", IEICE Trans. Fundamentals, pp. 1652-1658, October 1993.
 
12
Irith Pomeranz , Lakshmi N. Reddy , Sudhakar M. Reddy, COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits, Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner, p.194-203, October 26-30, 1991
 
13
M.H. Schulz, E. Trischler, and T. M. Sarfert, "SOCRATES: A highly efficient automatic test pattern generation system", IEEE Trans. on Computer-Aided Design, pp. 126-137, January 1988.
 
14
Gert-Jan Tromp, Minimal Test Sets for Combinatorial Circuits, Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner, p.204-209, October 26-30, 1991

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Krishnendu Chakrabarty, Optimal test access architectures for system-on-a-chip, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.6 n.1, p.26-49, Jan. 2001
A. Chandra , K. Chakrabarty, Efficient test data compression and decompression for system-on-a-chip using internal scan chains and Golomb coding, Proceedings of the conference on Design, automation and test in Europe, p.145-149, March 2001, Munich, Germany
Anshuman Chandra , Krishnendu Chakrabarty, Reduction of SOC test data volume, scan power and testing time using alternating run-length codes, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
Anshuman Chandra , Krishnendu Chakrabarty, Combining low-power scan testing and test data compression for system-on-a-chip, Proceedings of the 38th conference on Design automation, p.166-169, June 2001, Las Vegas, Nevada, United States
Makoto Sugihara , Hiroto Yasuura, Analysis and minimization of test time in a combined BIST and external test approach, Proceedings of the conference on Design, automation and test in Europe, p.134-140, March 27-30, 2000, Paris, France
Krishnendu Chakrabarty, Design of system-on-a-chip test access architectures under place-and-route and power constraints, Proceedings of the 37th conference on Design automation, p.432-437, June 05-09, 2000, Los Angeles, California, United States
Sudhakar M. Reddy , Kohei Miyase , Seiji Kajihara , Irith Pomeranz, On test data volume reduction for multiple scan chain designs, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.8 n.4, p.460-469, October 2003
Aiman H. El-Maleh , Yahya E. Osais, Test vector decomposition-based static compaction algorithms for combinational circuits, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.8 n.4, p.430-459, October 2003
Wenjing Rao , Ismet Bayraktaroglu , Alex Orailoglu, Test application time and volume compression through seed overlapping, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
Ismet Bayraktaroglu , Alex Orailoglu, Concurrent Application of Compaction and Compression for Test Time and Data Volume Reduction in Scan Designs, IEEE Transactions on Computers, v.52 n.11, p.1480-1489, November 2003
Ismet Bayraktaroglu , Alex Orailoglu, Test volume and application time reduction through scan chain concealment, Proceedings of the 38th conference on Design automation, p.151-155, June 2001, Las Vegas, Nevada, United States
Anshuman Chandra , Krishnendu Chakrabarty, Test Data Compression and Test Resource Partitioning for System-on-a-Chip Using Frequency-Directed Run-Length (FDR) Codes, IEEE Transactions on Computers, v.52 n.8, p.1076-1088, August 2003
Anshuman Chandra , Krishnendu Chakrabarty, Test Resource Partitioning for SOCs, IEEE Design & Test, v.18 n.5, p.80-91, September 2001
O. Novák , Z. Plíva , J. Nosek , A. Hlawiczka , T. Garbolino , K. Gucwa, Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor, Journal of Electronic Testing: Theory and Applications, v.20 n.1, p.109-122, February 2004
Xiaoyun Sun , Larry Kinney , Bapiraju Vinnakota, Combining dictionary coding and LFSR reseeding for test data compression, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
Terumine Hayashi , Haruna Yoshioka , Tsuyoshi Shinogi , Hidehiko Kita , Haruhiko Takase, Test data compression technique using selective don't-care identification, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.230-233, January 27-30, 2004, Yokohama, Japan
Anshuman Chandra , Krishnendu Chakrabarty, Analysis of Test Application Time for Test Data Compression Methods Based on Compression Codes, Journal of Electronic Testing: Theory and Applications, v.20 n.2, p.199-212, April 2004
Irith Pomeranz , Sudhakar M. Reddy, Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Nonscan Input Sequences and a Lower Bound on the Number of Tests, IEEE Transactions on Computers, v.53 n.12, p.1569-1581, December 2004
Lei Li , Krishnendu Chakrabarty , Nur A. Touba, Test data compression using dictionaries with selective entries and fixed-length indices, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.8 n.4, p.470-490, October 2003
Hamidreza Hashempour , Luca Schiano , Fabrizio Lombardi, Enhancing error resilience for reliable compression of VLSI test data, Proceedings of the 15th ACM Great Lakes symposium on VLSI, April 17-19, 2005, Chicago, Illinois, USA
Lei Li , Krishnendu Chakrabarty, On Using Exponential-Golomb Codes and Subexponential Codes for System-on-a-Chip Test Data Compression, Journal of Electronic Testing: Theory and Applications, v.20 n.6, p.667-670, December 2004
Seiji Kajihara , Masayasu Fukunaga , Xiaoqing Wen , Toshiyuki Maeda , Shuji Hamada , Yasuo Sato, Path delay test compaction with process variation tolerance, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
Masayasu Fukunaga , Seiji Kajihara , Xiaoqing Wen , Toshiyuki Maeda , Shuji Hamada , Yasuo Sato, A dynamic test compaction procedure for high-quality path delay testing, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
Youhua Shi , Nozomu Togawa , Shinji Kimura , Masao Yanagisawa , Tatsuo Ohtsuki, FCSCAN: an efficient multiscan-based test compression technique for test cost reduction, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
Yasumi Doi , Seiji Kajihara , Xiaoqing Wen , Lei Li , Krishnendu Chakrabarty, Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
Rainer Dorsch , Hans-Joachim Wunderlich, Reusing Scan Chains for Test Pattern Decompression, Journal of Electronic Testing: Theory and Applications, v.18 n.2, p.231-240, April 2002
Yin-He Han , Xiao-Wei Li , Hua-Wei Li , Anshuman Chandra, Test resource partitioning based on efficient response compaction for test time and tester channels reduction, Journal of Computer Science and Technology, v.20 n.2, p.201-209, March 2005
Terumine Hayashi , Haruna Yoshioka , Tsuyoshi Shinogi , Hidehiko Kita , Haruhiko Takase, On test data compression using selective don't-care identification, Journal of Computer Science and Technology, v.20 n.2, p.210-215, March 2005
Wei Wang , Yu Hu , Yin-He Han , Xiao-Wei Li , You-Sheng Zhang, Leakage current optimization techniques during test based on don't care bits assignment, Journal of Computer Science and Technology, v.22 n.5, p.673-680, September 2007
Gang Zeng , Hideo Ito, Concurrent core test for SOC using shared test set and scan chain disable, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
Irith Pomeranz , Sudhakar M. Reddy, On test generation by input cube avoidance, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
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Xiaoyu Ruan , Rajendra S. Katti, Data-Independent Pattern Run-Length Compression for Testing Embedded Cores in SoCs, IEEE Transactions on Computers, v.56 n.4, p.545-556, April 2007
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Irith Pomeranz , Sudhakar M. Reddy, The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits, Proceedings of the conference on Design, Automation and Test in Europe, p.1008-1013, March 07-11, 2005
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INDEX TERMS

Primary Classification:
  G. Mathematics of Computing
  G.2 DISCRETE MATHEMATICS

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)
  B.8 Performance and Reliability

  G. Mathematics of Computing
  G.4 MATHEMATICAL SOFTWARE
      Subjects: Algorithm design and analysis


General Terms:
Algorithms, Design, Experimentation, Measurement, Performance, Theory, Verification

Collaborative Colleagues:
Ilker Hamzaoglu: colleagues
Janak H. Patel: colleagues

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