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CITED BY 87
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I-Min Liu , Adnan Aziz , D. F. Wong, Meeting delay constraints in DSM by minimal repeater insertion, Proceedings of the conference on Design, automation and test in Europe, p.436-440, March 27-30, 2000, Paris, France
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Andrew E. Caldwell , Andrew B. Kahng , Igor L. Markov, Hypergraph partitioning with fixed vertices, Proceedings of the 36th ACM/IEEE conference on Design automation, p.355-359, June 21-25, 1999, New Orleans, Louisiana, United States
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Prashant Saxena , Noel Menezes , Pasquale Cocchini , Desmond A. Kirkpatrick, The scaling challenge: can correct-by-construction design help?, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA
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Ron Ho , Ken Mai , Hema Kapadia , Mark Horowitz, Interconnect scaling implications for CAD, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.425-429, November 07-11, 1999, San Jose, California, United States
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Tycho van Meeuwen , Arnout Vandecappelle , Allert van Zelst , Francky Catthoor , Diederik Verkest, System-level interconnect architecture exploration for custom memory organizations, Proceedings of the 14th international symposium on Systems synthesis, September 30-October 03, 2001, Montréal, P.Q., Canada
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Ron Ho , Ken Mai , Hema Kapadia , Mark Horowitz, Interconnect scaling implications for CAD, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.425-429, November 07-11, 1999, San Jose, California, United States
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Atsushi Sakai , Takashi Yamada , Yoshifumi Matsushita , Hiroto Yasuura, Routing methodology for minimizing 1nterconnect energy dissipation, Proceedings of the 13th ACM Great Lakes symposium on VLSI, April 28-29, 2003, Washington, D. C., USA
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Padmini Gopalakrishnan , Altan Odabasioglu , Lawrence Pileggi , Salil Raje, Overcoming wireload model uncertainty during physical design, Proceedings of the 2001 international symposium on Physical design, p.182-189, April 01-04, 2001, Sonoma, California, United States
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Sunil P. Khatri , Amit Mehrotra , Robert K. Brayton , Ralf H. J. M. Otten , Alberto Sangiovanni-Vincentelli, A novel VLSI layout fabric for deep sub-micron applications, Proceedings of the 36th ACM/IEEE conference on Design automation, p.491-496, June 21-25, 1999, New Orleans, Louisiana, United States
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Michael Orshansky , Linda Milor , Pinhong Chen , Kurt Keutzer , Chenming Hu, Impact of systematic spatial intra-chip gate length variability on performance of high-speed digital circuits, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
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Daehong Kim , Jinyong Jung , Sunghyun Lee , Jinhwan Jeon , Kiyoung Choi, Behavior-to-placed RTL synthesis with performance-driven placement, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
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Yu Cao , Chenming Hu , Xuejue Huang , Andrew B. Kahng , Sudhakar Muddu , Dirk Stroobandt , Dennis Sylvester, Effects of global interconnect optimizations on performance estimation of deep submicron design, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
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Sung-Woo Hur , Tung Cao , Karthik Rajagopal , Yegna Parasuram , Amit Chowdhary , Vladimir Tiourin , Bill Halpin, Force directed mongrel with physical net constraints, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
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Yu Cao , Chenming Hu , Xuejue Huang , Andrew B. Kahng , Igor L. Markov , Michael Oliver , Dirk Stroobandt , Dennis Sylvester, Improved a priori terconnect predictions and technology extrapolation in the GTX system, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.1, p.3-14, February 2003
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Karthik Rajagopal , Tal Shaked , Yegna Parasuram , Tung Cao , Amit Chowdhary , Bill Halpin, Timing driven force directed placement with physical net constraints, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA
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Dinesh Pamunuwa , Johnny Öberg , Li-Rong Zheng , Mikael Millberg , Axel Jantsch , Hannu Tenhunen, A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime, Integration, the VLSI Journal, v.38 n.1, p.3-17, October 2004
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Awet Yemane Weldezion , Matt Grange , Dinesh Pamunuwa , Zhonghai Lu , Axel Jantsch , Roshan Weerasekera , Hannu Tenhunen, Scalability of network-on-chip communication architecture for 3-D meshes, Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, p.114-123, May 10-13, 2009
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INDEX TERMS
Primary Classification:
B.
Hardware
B.7
INTEGRATED CIRCUITS
B.7.1
Types and Design Styles
Subjects:
Memory technologies
Additional Classification:
B.
Hardware
B.4
INPUT/OUTPUT AND DATA COMMUNICATIONS
B.8
Performance and Reliability
C.
Computer Systems Organization
C.1
PROCESSOR ARCHITECTURES
C.1.2
Multiple Data Stream Architectures (Multiprocessors)
Subjects:
Interconnection architectures (e.g., common bus, multiport memory, crossbar switch)
General Terms:
Design,
Measurement,
Performance,
Theory
Keywords:
ASIC,
CMOS scaling,
gate delay,
interconnect modeling,
power dissipation,
signal integrity,
wirelength
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